diff mbox series

[v1,19/29] target-microblaze: dec_msr: Fix MTS to FSR

Message ID 20180503091922.28733-20-edgar.iglesias@gmail.com
State New
Headers show
Series [v1,01/29] target-microblaze: dec_load: Use bool instead of unsigned int | expand

Commit Message

Edgar E. Iglesias May 3, 2018, 9:19 a.m. UTC 
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Fix moves to FSR. Not only bit 31 is accessible.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target/microblaze/translate.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

Comments

Richard Henderson May 3, 2018, 6:56 p.m. UTC | #1 
On 05/03/2018 02:19 AM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> 
> Fix moves to FSR. Not only bit 31 is accessible.
> 
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
>  target/microblaze/translate.c | 4 +---
>  1 file changed, 1 insertion(+), 3 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~
Alistair Francis May 3, 2018, 9:46 p.m. UTC | #2 
On Thu, May 3, 2018 at 2:38 AM Edgar E. Iglesias <edgar.iglesias@gmail.com>
wrote:

> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

> Fix moves to FSR. Not only bit 31 is accessible.

> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>   target/microblaze/translate.c | 4 +---
>   1 file changed, 1 insertion(+), 3 deletions(-)

> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> index 05449fb941..97d7782bc6 100644
> --- a/target/microblaze/translate.c
> +++ b/target/microblaze/translate.c
> @@ -533,11 +533,9 @@ static void dec_msr(DisasContext *dc)
>                   break;
>               case SR_EAR:
>               case SR_ESR:
> +            case SR_FSR:
>                   tcg_gen_mov_i32(cpu_SR[sr], cpu_R[dc->ra]);
>                   break;
> -            case 0x7:
> -                tcg_gen_andi_i32(cpu_SR[SR_FSR], cpu_R[dc->ra], 31);
> -                break;
>               case 0x800:
>                   tcg_gen_st_i32(cpu_R[dc->ra],
>                                  cpu_env, offsetof(CPUMBState, slr));
> --
> 2.14.1
diff mbox series

Patch

diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 05449fb941..97d7782bc6 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -533,11 +533,9 @@  static void dec_msr(DisasContext *dc)
                 break;
             case SR_EAR:
             case SR_ESR:
+            case SR_FSR:
                 tcg_gen_mov_i32(cpu_SR[sr], cpu_R[dc->ra]);
                 break;
-            case 0x7:
-                tcg_gen_andi_i32(cpu_SR[SR_FSR], cpu_R[dc->ra], 31);
-                break;
             case 0x800:
                 tcg_gen_st_i32(cpu_R[dc->ra],
                                cpu_env, offsetof(CPUMBState, slr));