Message ID | 20180430150837.20470-5-edgar.iglesias@gmail.com |
---|---|
State | New |
Headers | show |
Series | Xilinx queue 2018-04-30 | expand |
diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index a0f06758f8..8391811900 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -182,7 +182,7 @@ done: uint32_t mmu_read(CPUMBState *env, uint32_t rn) { unsigned int i; - uint32_t r; + uint32_t r = 0; if (env->mmu.c_mmu < 2 || !env->mmu.c_mmu_tlb_access) { qemu_log_mask(LOG_GUEST_ERROR, "MMU access on MMU-less system\n"); @@ -211,6 +211,9 @@ uint32_t mmu_read(CPUMBState *env, uint32_t rn) } r = env->mmu.regs[rn]; break; + case MMU_R_TLBSX: + qemu_log_mask(LOG_GUEST_ERROR, "TLBSX is write-only.\n"); + break; default: r = env->mmu.regs[rn]; break;