diff mbox series

[v2,5/5] target-microblaze: mmu: Make the TLBX MISS bit read-only

Message ID 20180423123225.30503-6-edgar.iglesias@gmail.com
State New
Headers show
Series target-microblaze: Misc bug fixes | expand

Commit Message

Edgar E. Iglesias April 23, 2018, 12:32 p.m. UTC 
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Make the TLBX MISS bit read-only.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target/microblaze/mmu.c | 4 ++++
 1 file changed, 4 insertions(+)

Comments

Richard Henderson April 23, 2018, 7:33 p.m. UTC | #1 
On 04/23/2018 02:32 AM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> 
> Make the TLBX MISS bit read-only.
> 
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
>  target/microblaze/mmu.c | 4 ++++
>  1 file changed, 4 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~
diff mbox series

Patch

diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c
index 8391811900..9d5e6aa8a5 100644
--- a/target/microblaze/mmu.c
+++ b/target/microblaze/mmu.c
@@ -273,6 +273,10 @@  void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
                 env->mmu.regs[rn] = v;
             }
             break;
+        case MMU_R_TLBX:
+            /* Bit 31 is read-only.  */
+            env->mmu.regs[rn] = deposit32(env->mmu.regs[rn], 0, 31, v);
+            break;
         case MMU_R_TLBSX:
         {
             struct microblaze_mmu_lookup lu;