From patchwork Tue Feb 9 15:24:49 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Hogan X-Patchwork-Id: 580895 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3F50A1402D2 for ; Wed, 10 Feb 2016 02:25:38 +1100 (AEDT) Received: from localhost ([::1]:57019 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aTAAa-0003iZ-AO for incoming@patchwork.ozlabs.org; Tue, 09 Feb 2016 10:25:36 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55249) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aTA9x-0002by-Ug for qemu-devel@nongnu.org; Tue, 09 Feb 2016 10:25:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aTA9u-00067b-Jt for qemu-devel@nongnu.org; Tue, 09 Feb 2016 10:24:57 -0500 Received: from mailapp01.imgtec.com ([195.59.15.196]:6935 helo=imgpgp01.kl.imgtec.org) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aTA9u-000675-BL for qemu-devel@nongnu.org; Tue, 09 Feb 2016 10:24:54 -0500 Received: from imgpgp01.kl.imgtec.org (imgpgp01.kl.imgtec.org [127.0.0.1]) by imgpgp01.kl.imgtec.org (PGP Universal) with ESMTP id 7EF9541F8D2E; Tue, 9 Feb 2016 15:24:50 +0000 (GMT) Received: from mailapp01.imgtec.com ([10.100.180.242]) by imgpgp01.kl.imgtec.org (PGP Universal service); Tue, 09 Feb 2016 15:24:50 +0000 X-PGP-Universal: processed; by imgpgp01.kl.imgtec.org on Tue, 09 Feb 2016 15:24:50 +0000 Received: from HHMAIL01.hh.imgtec.org (unknown [10.100.10.19]) by Websense Email Security Gateway with ESMTPS id 0A9F6754CDF14; Tue, 9 Feb 2016 15:24:48 +0000 (GMT) Received: from LEMAIL01.le.imgtec.org (192.168.152.62) by HHMAIL01.hh.imgtec.org (10.100.10.19) with Microsoft SMTP Server (TLS) id 14.3.266.1; Tue, 9 Feb 2016 15:24:50 +0000 Received: from localhost (192.168.154.110) by LEMAIL01.le.imgtec.org (192.168.152.62) with Microsoft SMTP Server (TLS) id 14.3.210.2; Tue, 9 Feb 2016 15:24:49 +0000 Date: Tue, 9 Feb 2016 15:24:49 +0000 From: James Hogan To: Richard Henderson Message-ID: <20160209152449.GA3678@jhogan-linux.le.imgtec.org> References: <1455014403-10742-1-git-send-email-rth@twiddle.net> <1455014403-10742-3-git-send-email-rth@twiddle.net> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1455014403-10742-3-git-send-email-rth@twiddle.net> User-Agent: Mutt/1.5.23 (2014-03-12) X-Originating-IP: [192.168.154.110] X-ESG-ENCRYPT-TAG: 30575414 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x X-Received-From: 195.59.15.196 Cc: qemu-devel@nongnu.org, aurelien@aurel32.net Subject: Re: [Qemu-devel] [PATCH 02/15] tcg-mips: Support 64-bit opcodes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Hi Richard, Awesome, thanks for looking at these patches again :-) On Tue, Feb 09, 2016 at 09:39:50PM +1100, Richard Henderson wrote: > +#if !use_mips32r6_instructions > + { INDEX_op_muls2_i64, { "r", "r", "rZ", "rZ" } }, > + { INDEX_op_mulu2_i64, { "r", "r", "rZ", "rZ" } }, > +#endif this... > +#define TCG_TARGET_HAS_mulu2_i64 1 > +#define TCG_TARGET_HAS_muls2_i64 1 and this are inconsistent for r6: Missing op definition for mulu2_i64 Missing op definition for muls2_i64 /work/mips/qemu/main/tcg/tcg.c:1253: tcg fatal error It gets further (to the point of seg faulting - looking into it) with this fixup: Cheers James diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 374d80374021..fa9cd4ab296a 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -145,8 +145,8 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_nand_i64 0 #define TCG_TARGET_HAS_add2_i64 0 #define TCG_TARGET_HAS_sub2_i64 0 -#define TCG_TARGET_HAS_mulu2_i64 1 -#define TCG_TARGET_HAS_muls2_i64 1 +#define TCG_TARGET_HAS_mulu2_i64 (!use_mips32r6_instructions) +#define TCG_TARGET_HAS_muls2_i64 (!use_mips32r6_instructions) #define TCG_TARGET_HAS_muluh_i64 1 #define TCG_TARGET_HAS_mulsh_i64 1 #define TCG_TARGET_HAS_ext32s_i64 1