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[52.8.89.49]) by smtp.gmail.com with ESMTPSA id m75sm16327605pfj.38.2016.01.15.07.37.43 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Fri, 15 Jan 2016 07:37:44 -0800 (PST) Date: Fri, 15 Jan 2016 16:37:37 +0100 From: "Edgar E. Iglesias" To: Peter Maydell Message-ID: <20160115153737.GL29396@toto> References: <1452796451-2946-1-git-send-email-peter.maydell@linaro.org> <1452796451-2946-2-git-send-email-peter.maydell@linaro.org> <20160115143836.GI29396@toto> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400e:c00::244 Cc: Paolo Bonzini , qemu-arm , Alex =?iso-8859-1?Q?Benn=E9e?= , QEMU Developers , Patch Tracking Subject: Re: [Qemu-devel] [PATCH 1/8] target-arm: Properly support EL2 and EL3 in arm_el_is_aa64() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org On Fri, Jan 15, 2016 at 02:50:24PM +0000, Peter Maydell wrote: > On 15 January 2016 at 14:38, Edgar E. Iglesias wrote: > > On Thu, Jan 14, 2016 at 06:34:04PM +0000, Peter Maydell wrote: > >> Support EL2 and EL3 in arm_el_is_aa64() by implementing the > >> logic for checking the SCR_EL3 and HCR_EL2 register-width bits > >> as appropriate to determine the register width of lower exception > >> levels. > >> > >> Signed-off-by: Peter Maydell > > > > Hi Peter, > > > > On the ZynqMP we've got the Cortex-A53 EL3 RW configurable at reset > > time. At some later point we'll likely have to implement that > > runtime option... > > That might be tricky, we fairly well bake in "AARCH64 feature means > 64-bit highest EL" at the moment. The KVM code takes the approach > of "if it's not going to reset in AArch64 then unset the feature bit". > > Anyway, we'll cross that bridge when we get to it. > > Do you have much locally extra that you needed for enabling > EL3 in the Cortex-A53? I have an ARM Trusted Firmware + OP-TEE > setup now that I'm going to use to work through the missing bits, > but if you've already gone through that effort there's no need > my duplicating work... I don't have anything immediate for EL3 beyond enabling it and some boot thing for a15/aarch32 to allow me to run my tests. I haven't really looked at the boot in detail for aa32 so I haven't bothered submitting it. This is it: commit b30c7102624241a67ebb2d3df70e88a4148f68a4 Author: Edgar E. Iglesias Date: Sun Sep 13 09:52:01 2015 +0200 target-arm: Start EL3 capable ARMv7 cores in MON mode Signed-off-by: Edgar E. Iglesias diff --git a/target-arm/cpu.c b/target-arm/cpu.c index f6f5539..485965f 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -164,6 +164,9 @@ static void arm_cpu_reset(CPUState *s) #else /* SVC mode with interrupts disabled. */ env->uncached_cpsr = ARM_CPU_MODE_SVC; + if (arm_feature(env, ARM_FEATURE_EL3)) { + env->uncached_cpsr = ARM_CPU_MODE_MON; + } env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is * clear at reset. Initial SP and PC are loaded from ROM.