From patchwork Fri May 9 18:15:39 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavel Pisa X-Patchwork-Id: 347502 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 5DAAB1400A0 for ; Sat, 10 May 2014 04:47:35 +1000 (EST) Received: from localhost ([::1]:54028 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WippV-0000JH-Ba for incoming@patchwork.ozlabs.org; Fri, 09 May 2014 14:47:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60518) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wipon-0007dY-RS for qemu-devel@nongnu.org; Fri, 09 May 2014 14:46:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Wipoa-000080-6C for qemu-devel@nongnu.org; Fri, 09 May 2014 14:46:49 -0400 Received: from relay.felk.cvut.cz ([2001:718:2:1611:0:1:0:70]:40842) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WipoZ-00007R-CQ for qemu-devel@nongnu.org; Fri, 09 May 2014 14:46:36 -0400 Received: from cmp.felk.cvut.cz (haar.felk.cvut.cz [147.32.84.19]) by relay.felk.cvut.cz (8.14.8/8.14.8) with ESMTP id s49IFeHU042456; Fri, 9 May 2014 20:15:40 +0200 (CEST) (envelope-from pisa@cmp.felk.cvut.cz) Received: from haar.felk.cvut.cz (localhost [127.0.0.1]) by cmp.felk.cvut.cz (8.14.0/8.12.3/SuSE Linux 0.6) with ESMTP id s49IFeHX011656; Fri, 9 May 2014 20:15:40 +0200 Received: (from pisa@localhost) by haar.felk.cvut.cz (8.14.0/8.13.7/Submit) id s49IFeqi011654; Fri, 9 May 2014 20:15:40 +0200 X-Authentication-Warning: haar.felk.cvut.cz: pisa set sender to pisa@cmp.felk.cvut.cz using -f From: Pavel Pisa To: "qemu-devel@nongnu.org" , Oliver Hartkopp A , jinyang.sia@gmail.com Date: Fri, 9 May 2014 20:15:39 +0200 User-Agent: KMail/1.9.10 (enterprise35 0.20100827.1168748) References: <201405092010.19482.pisa@cmp.felk.cvut.cz> In-Reply-To: <201405092010.19482.pisa@cmp.felk.cvut.cz> X-KMail-QuotePrefix: > MIME-Version: 1.0 Content-Disposition: inline Message-Id: <201405092015.40107.pisa@cmp.felk.cvut.cz> X-FELK-MailScanner-Information: X-MailScanner-ID: s49IFeHU042456 X-FELK-MailScanner: Found to be clean X-FELK-MailScanner-SpamCheck: not spam, SpamAssassin (not cached, score=-1.151, required 6, autolearn=not spam, BAYES_00 -0.50, RP_MATCHES_RCVD -0.65) X-FELK-MailScanner-From: pisa@cmp.felk.cvut.cz X-FELK-MailScanner-Watermark: 1400264142.71113@oMuqV66IQstzcL4DV7y0Bg X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:718:2:1611:0:1:0:70 Cc: Stefan Weil , rtems-devel@rtems.org, Andreas =?iso-8859-1?q?F=E4rber?= , linux-can@vger.kernel.org Subject: [Qemu-devel] [PATCH 2/2] CAN bus Kvaser PCI CAN-S (single SJA1000 channel) emulation added. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Pavel Pisa --- hw/net/Makefile.objs | 1 + hw/net/can_kvaser_pci.c | 355 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 356 insertions(+) create mode 100644 hw/net/can_kvaser_pci.c diff --git a/hw/net/Makefile.objs b/hw/net/Makefile.objs index 28679fc..3d66ca9 100644 --- a/hw/net/Makefile.objs +++ b/hw/net/Makefile.objs @@ -27,6 +27,7 @@ common-obj-$(CONFIG_LANCE) += lance.o obj-$(CONFIG_CAN_SJA1000) += can_core.o obj-$(CONFIG_CAN_SJA1000) += can_sja1000.o obj-$(CONFIG_CAN_PCI) += can_pci.o +obj-$(CONFIG_CAN_PCI) += can_kvaser_pci.o obj-$(CONFIG_ETRAXFS) += etraxfs_eth.o obj-$(CONFIG_COLDFIRE) += mcf_fec.o diff --git a/hw/net/can_kvaser_pci.c b/hw/net/can_kvaser_pci.c new file mode 100644 index 0000000..b76de5f --- /dev/null +++ b/hw/net/can_kvaser_pci.c @@ -0,0 +1,355 @@ +/* + * Kvaser PCI CAN device (SJA1000 based) emulation + * + * Copyright (c) 2013-2014 Jin Yang + * Copyright (c) 2014 Pavel Pisa + * + * Partially based on educational PCIexpress APOHW hardware + * emulator used fro class A0B36APO at CTU FEE course by + * Rostislav Lisovy and Pavel Pisa + * + * Initial development supported by Google GSoC 2013 from RTEMS project slot + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "hw/hw.h" +#include "hw/pci/pci.h" +#include "qemu/event_notifier.h" +#include "qemu/osdep.h" +#include "qemu/thread.h" +#include "qemu/sockets.h" +#include "sysemu/char.h" +#include "net/can_emu.h" + +#include "can_sja1000.h" + +#define TYPE_CAN_PCI_DEV "kvaser_pci" + +#define KVASER_PCI_DEV(obj) \ + OBJECT_CHECK(KvaserPCIState, (obj), TYPE_CAN_PCI_DEV) + +#ifndef KVASER_PCI_VENDOR_ID1 +#define KVASER_PCI_VENDOR_ID1 0x10e8 /* the PCI device and vendor IDs */ +#endif + +#ifndef KVASER_PCI_DEVICE_ID1 +#define KVASER_PCI_DEVICE_ID1 0x8406 +#endif + +#define KVASER_PCI_S5920_RANGE 0x80 +#define KVASER_PCI_SJA_RANGE 0x80 +#define KVASER_PCI_XILINX_RANGE 0x8 + +#define KVASER_PCI_BYTES_PER_SJA 0x20 + +#define S5920_OMB 0x0C +#define S5920_IMB 0x1C +#define S5920_MBEF 0x34 +#define S5920_INTCSR 0x38 +#define S5920_RCR 0x3C +#define S5920_PTCR 0x60 + +#define S5920_INTCSR_ADDON_INTENABLE_M 0x2000 +#define S5920_INTCSR_INTERRUPT_ASSERTED_M 0x800000 + +#define KVASER_PCI_XILINX_VERINT 7 /* Lower nibble simulate interrupts, + high nibble version number. */ + +typedef struct KvaserPCIState { + /*< private >*/ + PCIDevice dev; + /*< public >*/ + MemoryRegion s5920_io; + MemoryRegion sja_io; + MemoryRegion xilinx_io; + + CanSJA1000State sja_state; + qemu_irq irq; + + uint32_t s5920_intcsr; + uint32_t s5920_irqstate; + + char *model; /* The model that support, only SJA1000 now. */ + char *canbus; + char *host; +} KvaserPCIState; + +static void kvaser_pci_irq_raise(void *opaque) +{ + KvaserPCIState *d = (KvaserPCIState *)opaque; + d->s5920_irqstate = 1; + + if (d->s5920_intcsr & S5920_INTCSR_ADDON_INTENABLE_M) + qemu_irq_raise(d->irq); +} + +static void kvaser_pci_irq_lower(void *opaque) +{ + KvaserPCIState *d = (KvaserPCIState *)opaque; + d->s5920_irqstate = 0; + qemu_irq_lower(d->irq); +} + +static void +kvaser_pci_reset(void *opaque) +{ + KvaserPCIState *d = (KvaserPCIState *)opaque; + CanSJA1000State *s = &d->sja_state; + + can_sja_hardware_reset(s); +} + +static uint64_t kvaser_pci_s5920_io_read(void *opaque, hwaddr addr, unsigned size) +{ + KvaserPCIState *d = opaque; + uint64_t val; + + switch (addr) { + case S5920_INTCSR: + val = d->s5920_intcsr; + val &= ~S5920_INTCSR_INTERRUPT_ASSERTED_M; + if (d->s5920_irqstate) + val |= S5920_INTCSR_INTERRUPT_ASSERTED_M; + return val; + } + return 0; +} + +static void kvaser_pci_s5920_io_write(void *opaque, hwaddr addr, uint64_t data, + unsigned size) +{ + KvaserPCIState *d = opaque; + + switch (addr) { + case S5920_INTCSR: + if (~d->s5920_intcsr & data & S5920_INTCSR_ADDON_INTENABLE_M) + if (d->s5920_irqstate) + qemu_irq_raise(d->irq); + d->s5920_intcsr = data; + break; + } +} + +static uint64_t kvaser_pci_sja_io_read(void *opaque, hwaddr addr, unsigned size) +{ + KvaserPCIState *d = opaque; + CanSJA1000State *s = &d->sja_state; + + if (addr >= KVASER_PCI_BYTES_PER_SJA) + return 0; + + return can_sja_mem_read(s, addr, size); +} + +static void kvaser_pci_sja_io_write(void *opaque, hwaddr addr, uint64_t data, + unsigned size) +{ + KvaserPCIState *d = opaque; + CanSJA1000State *s = &d->sja_state; + + if (addr >= KVASER_PCI_BYTES_PER_SJA) + return; + + can_sja_mem_write(s, addr, data, size); +} + +static uint64_t kvaser_pci_xilinx_io_read(void *opaque, hwaddr addr, unsigned size) +{ + /*KvaserPCIState *d = opaque;*/ + + switch (addr) { + case KVASER_PCI_XILINX_VERINT: + return (13 << 4) | 0; + } + + return 0; +} + +static void kvaser_pci_xilinx_io_write(void *opaque, hwaddr addr, uint64_t data, + unsigned size) +{ + /*KvaserPCIState *d = opaque;*/ +} + +static const MemoryRegionOps kvaser_pci_s5920_io_ops = { + .read = kvaser_pci_s5920_io_read, + .write = kvaser_pci_s5920_io_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, +}; + +static const MemoryRegionOps kvaser_pci_sja_io_ops = { + .read = kvaser_pci_sja_io_read, + .write = kvaser_pci_sja_io_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .impl = { + .min_access_size = 1, + .max_access_size = 1, + }, +}; + +static const MemoryRegionOps kvaser_pci_xilinx_io_ops = { + .read = kvaser_pci_xilinx_io_read, + .write = kvaser_pci_xilinx_io_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .impl = { + .min_access_size = 1, + .max_access_size = 1, + }, +}; + +static int kvaser_pci_init(PCIDevice *pci_dev) +{ + KvaserPCIState *d = KVASER_PCI_DEV(pci_dev); + CanSJA1000State *s = &d->sja_state; + uint8_t *pci_conf; + CanBusState *can_bus; + + if (d->model) { + if (strncmp(d->model, "pcican-s", 256)) { /* for security reason */ + qerror_report(ERROR_CLASS_GENERIC_ERROR, + "Can't create CAN device, the model %s is not supported now.\n", d->model); + exit(1); + } + } + + can_bus = can_bus_find_by_name(d->canbus, true); + if (can_bus == NULL) { + qerror_report(ERROR_CLASS_GENERIC_ERROR, "Cannot create can find/allocate CAN bus\n"); + exit(1); + + } + + if (d->host != NULL) { + if (can_bus_connect_to_host_device(can_bus, d->host) < 0) { + qerror_report(ERROR_CLASS_GENERIC_ERROR, "Cannot connect CAN bus to host device \"%s\"\n", d->host); + exit(1); + } + } + + pci_conf = pci_dev->config; + pci_conf[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */ + + d->irq = pci_allocate_irq(&d->dev); + + can_sja_init(s, kvaser_pci_irq_raise, kvaser_pci_irq_lower, d); + + qemu_register_reset(kvaser_pci_reset, d); + + if (can_sja_connect_to_bus(s, can_bus) < 0) { + qerror_report(ERROR_CLASS_GENERIC_ERROR, + "can_sja_connect_to_bus failed\n"); + exit(1); + } + + memory_region_init_io(&d->s5920_io, OBJECT(d), &kvaser_pci_s5920_io_ops, d, + "kvaser_pci-s5920", KVASER_PCI_S5920_RANGE); + memory_region_init_io(&d->sja_io, OBJECT(d), &kvaser_pci_sja_io_ops, d, + "kvaser_pci-sja", KVASER_PCI_SJA_RANGE); + memory_region_init_io(&d->xilinx_io, OBJECT(d), &kvaser_pci_xilinx_io_ops, d, + "kvaser_pci-xilinx", KVASER_PCI_XILINX_RANGE); + + pci_register_bar(&d->dev, /*BAR*/ 0, PCI_BASE_ADDRESS_SPACE_IO, &d->s5920_io); + pci_register_bar(&d->dev, /*BAR*/ 1, PCI_BASE_ADDRESS_SPACE_IO, &d->sja_io); + pci_register_bar(&d->dev, /*BAR*/ 2, PCI_BASE_ADDRESS_SPACE_IO, &d->xilinx_io); + + return 0; +} + +static void kvaser_pci_exit(PCIDevice *pci_dev) +{ + KvaserPCIState *d = KVASER_PCI_DEV(pci_dev); + CanSJA1000State *s = &d->sja_state; + + can_sja_disconnect(s); + + qemu_unregister_reset(kvaser_pci_reset, d); + + memory_region_destroy(&d->s5920_io); + memory_region_destroy(&d->sja_io); + memory_region_destroy(&d->xilinx_io); + + can_sja_exit(s); + + qemu_free_irq(d->irq); +} + +static const VMStateDescription vmstate_kvaser_pci = { + .name = "kvaser_pci", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField[]) { + VMSTATE_PCI_DEVICE(dev, KvaserPCIState), + VMSTATE_STRUCT(sja_state, KvaserPCIState, 0, vmstate_can_sja, CanSJA1000State), + /*char *model,*/ + VMSTATE_UINT32(s5920_intcsr, KvaserPCIState), + VMSTATE_UINT32(s5920_irqstate, KvaserPCIState), + VMSTATE_END_OF_LIST() + } +}; + +static void qdev_kvaser_pci_reset(DeviceState *dev) +{ + KvaserPCIState *d = KVASER_PCI_DEV(dev); + kvaser_pci_reset(d); +} + +static Property kvaser_pci_properties[] = { + DEFINE_PROP_STRING("canbus", KvaserPCIState, canbus), + DEFINE_PROP_STRING("host", KvaserPCIState, host), + DEFINE_PROP_STRING("model", KvaserPCIState, model), + DEFINE_PROP_END_OF_LIST(), +}; + +static void kvaser_pci_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + + k->init = kvaser_pci_init; + k->exit = kvaser_pci_exit; + k->vendor_id = KVASER_PCI_VENDOR_ID1; + k->device_id = KVASER_PCI_DEVICE_ID1; + k->revision = 0x00; + k->class_id = 0x00ff00; + dc->desc = "Kvaser PCICANx"; + dc->props = kvaser_pci_properties; + dc->vmsd = &vmstate_kvaser_pci; + set_bit(DEVICE_CATEGORY_MISC, dc->categories); + dc->reset = qdev_kvaser_pci_reset; +} + +static const TypeInfo kvaser_pci_info = { + .name = TYPE_CAN_PCI_DEV, + .parent = TYPE_PCI_DEVICE, + .instance_size = sizeof(KvaserPCIState), + .class_init = kvaser_pci_class_init, +}; + +static void kvaser_pci_register_types(void) +{ + type_register_static(&kvaser_pci_info); +} + +type_init(kvaser_pci_register_types)