From patchwork Mon Aug 2 13:58:58 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 60538 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 203381007D2 for ; Tue, 3 Aug 2010 00:13:25 +1000 (EST) Received: from localhost ([127.0.0.1]:33617 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Ofvla-0008Tk-3E for incoming@patchwork.ozlabs.org; Mon, 02 Aug 2010 10:13:22 -0400 Received: from [140.186.70.92] (port=33619 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Ofvjd-0007ij-Dm for qemu-devel@nongnu.org; Mon, 02 Aug 2010 10:11:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1Ofvjb-0002fV-W9 for qemu-devel@nongnu.org; Mon, 02 Aug 2010 10:11:21 -0400 Received: from mail-bw0-f45.google.com ([209.85.214.45]:41806) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1Ofvjb-0002f9-NS for qemu-devel@nongnu.org; Mon, 02 Aug 2010 10:11:19 -0400 Received: by bwz16 with SMTP id 16so1761911bwz.4 for ; Mon, 02 Aug 2010 07:11:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:date:from:to:subject :message-id:mime-version:content-type:content-disposition:user-agent; bh=47rdGZyWn5kIyzoY2BQ9/CN0A5xsbiATxzB/xujgu6Y=; b=kVsCR5TDefx2TMC612Hhlsb7cVBVJ0F2e4Fee56Bq3BIMRUKnss+FrGUEbnFD9UINw Y0RRXtl3tIA59/A6u72EbhQI5zXbGEOxfE9ErXrm0hbHTl5nV+FJunNxzwl9T34mRsB7 PGzXyQdpu4Ths1dr/Xqw93OgPea+P6k/8k9R0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=date:from:to:subject:message-id:mime-version:content-type :content-disposition:user-agent; b=VDmJjtU1W9F3LIm1LHJgAIiupi4TP5ISqi4mB9xGXRZf1/jUE6GdsoUPaiNu90zK0k Zy8IoX6M1fPYRmuQJZWVlYgHNNk50OfDcTiYt2yJkqVc6+Y9E/wBipCYkuUo0zD7QGYL Gjf1lBc9klzM6qwPfBzC3q9xlZ2Wg3e3i75cM= Received: by 10.204.179.194 with SMTP id br2mr4128509bkb.196.1280758277671; Mon, 02 Aug 2010 07:11:17 -0700 (PDT) Received: from localhost (proxy.se.axis.com [195.60.68.148]) by mx.google.com with ESMTPS id o20sm4146578bkw.3.2010.08.02.07.11.14 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 02 Aug 2010 07:11:14 -0700 (PDT) Date: Mon, 2 Aug 2010 15:58:58 +0200 From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Message-ID: <20100802135858.GA5351@edde.se.axis.com> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.20 (2009-06-14) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) Subject: [Qemu-devel] [PATCH] MIPS support for VInt and VEIC interrupt modes. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Hi, This patch adds the final bits for supporting Vectored Interrupts on MIPS. I also added VEIC mode, but only the logic that is part of the CPU. VInt is the mode where the MIPS internally computes a 3 bit (0-7) vector from the 8 hw interrupt lines. VEIC is the mode where an external interrupt controller computes the vector and communicates it through the IPL lines in the Cause reg. VInt was tested by booting a linux-2.6.33 kernel, again on an out-of-tree board. I also ran the images on the wiki to check for regressions in the compat interrupt mode. VEIC was very lightly tested, I dont have emulation of all the necessary blocks to boot linux on a VEIC MIPS guest yet. I tested the CPU parts with a couple of small synthetic irq test cases. BTW, the way I configure VInt/VEIC is to have the board setup reconfigure the MIPS configure bits at reset. That's why there are no changes to target-mips/translate_init.c. Comments? Cheers commit 234705e71642741ad4b8762dfb40969406d7c1ea Author: Edgar E. Iglesias Date: Mon Aug 2 15:50:39 2010 +0200 mips: Add support for VInt and VEIC irq modes. Signed-off-by: Edgar E. Iglesias diff --git a/cpu-exec.c b/cpu-exec.c index d170566..dbdfdcc 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -448,7 +448,7 @@ int cpu_exec(CPUState *env1) } #elif defined(TARGET_MIPS) if ((interrupt_request & CPU_INTERRUPT_HARD) && - (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) && + cpu_mips_hw_interrupts_pending(env) && (env->CP0_Status & (1 << CP0St_IE)) && !(env->CP0_Status & (1 << CP0St_EXL)) && !(env->CP0_Status & (1 << CP0St_ERL)) && diff --git a/target-mips/cpu.h b/target-mips/cpu.h index b8e6fee..d2fe925 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -525,6 +525,29 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) env->active_tc.gpr[2] = 0; } +static inline int cpu_mips_hw_interrupts_pending(CPUState *env) +{ + int32_t pending; + int32_t status; + int r; + + pending = env->CP0_Cause & CP0Ca_IP_mask; + status = env->CP0_Status & CP0Ca_IP_mask; + + if (env->CP0_Config3 & (1 << CP0C3_VEIC)) { + /* A MIPS configured with a vectorizing external interrupt controller + will feed a vector into the Cause pending lines. The core treats + the status_lines as a vector level, not as indiviual masks. */ + r = pending > status; + } else { + /* A MIPS configured with compatibility or VInt (Vectored Interrupts) + treats the pending lines as individual interrupt lines, the status + lines are individual masks. */ + r = pending & status; + } + return r; +} + #include "cpu-all.h" /* Memory access type : diff --git a/target-mips/helper.c b/target-mips/helper.c index de2ed7d..bdc1e53 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -478,6 +478,33 @@ void do_interrupt (CPUState *env) cause = 0; if (env->CP0_Cause & (1 << CP0Ca_IV)) offset = 0x200; + + if (env->CP0_Config3 & ((1 << CP0C3_VInt) | (1 << CP0C3_VEIC))) { + /* Vectored Interrupts. */ + unsigned int spacing; + unsigned int vector; + unsigned int pending = (env->CP0_Cause & CP0Ca_IP_mask) >> 8; + + /* Compute the Vector Spacing. */ + spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & ((1 << 6) - 1); + spacing <<= 5; + + if (env->CP0_Config3 & (1 << CP0C3_VInt)) { + /* For VInt mode, the MIPS computes the vector internally. */ + for (vector = 0; vector < 8; vector++) { + if (pending & 1) { + /* Found it. */ + break; + } + pending >>= 1; + } + } else { + /* For VEIC mode, the external interrupt controller feeds the + vector throught the CP0Cause IP lines. */ + vector = pending; + } + offset = 0x200 + vector * spacing; + } goto set_EPC; case EXCP_LTLBL: cause = 1;