diff mbox

MIPS support for VInt and VEIC interrupt modes.

Message ID 20100802135858.GA5351@edde.se.axis.com
State New
Headers show

Commit Message

Edgar E. Iglesias Aug. 2, 2010, 1:58 p.m. UTC 
Hi,

This patch adds the final bits for supporting Vectored Interrupts 
on MIPS. I also added VEIC mode, but only the logic that is part of the CPU.

VInt is the mode where the MIPS internally computes a 3 bit (0-7) vector
from the 8 hw interrupt lines.
VEIC is the mode where an external interrupt controller computes the vector
and communicates it through the IPL lines in the Cause reg.

VInt was tested by booting a linux-2.6.33 kernel, again on an out-of-tree
board. I also ran the images on the wiki to check for regressions in the
compat interrupt mode.

VEIC was very lightly tested, I dont have emulation of all the necessary
blocks to boot linux on a VEIC MIPS guest yet. I tested the CPU parts with a
couple of small synthetic irq test cases.

BTW, the way I configure VInt/VEIC is to have the board setup reconfigure
the MIPS configure bits at reset. That's why there are no changes to 
target-mips/translate_init.c.

Comments?

Cheers

commit 234705e71642741ad4b8762dfb40969406d7c1ea
Author: Edgar E. Iglesias <edgar@axis.com>
Date:   Mon Aug 2 15:50:39 2010 +0200

    mips: Add support for VInt and VEIC irq modes.
    
    Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
diff mbox

Patch

diff --git a/cpu-exec.c b/cpu-exec.c
index d170566..dbdfdcc 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -448,7 +448,7 @@  int cpu_exec(CPUState *env1)
                     }
 #elif defined(TARGET_MIPS)
                     if ((interrupt_request & CPU_INTERRUPT_HARD) &&
-                        (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&
+                        cpu_mips_hw_interrupts_pending(env) &&
                         (env->CP0_Status & (1 << CP0St_IE)) &&
                         !(env->CP0_Status & (1 << CP0St_EXL)) &&
                         !(env->CP0_Status & (1 << CP0St_ERL)) &&
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index b8e6fee..d2fe925 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -525,6 +525,29 @@  static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
     env->active_tc.gpr[2] = 0;
 }
 
+static inline int cpu_mips_hw_interrupts_pending(CPUState *env)
+{
+    int32_t pending;
+    int32_t status;
+    int r;
+
+    pending = env->CP0_Cause & CP0Ca_IP_mask;
+    status = env->CP0_Status & CP0Ca_IP_mask;
+
+    if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
+        /* A MIPS configured with a vectorizing external interrupt controller
+           will feed a vector into the Cause pending lines. The core treats
+           the status_lines as a vector level, not as indiviual masks.  */
+        r = pending > status;
+    } else {
+        /* A MIPS configured with compatibility or VInt (Vectored Interrupts)
+           treats the pending lines as individual interrupt lines, the status
+           lines are individual masks.  */
+        r = pending & status;
+    }
+    return r;
+}
+
 #include "cpu-all.h"
 
 /* Memory access type :
diff --git a/target-mips/helper.c b/target-mips/helper.c
index de2ed7d..bdc1e53 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -478,6 +478,33 @@  void do_interrupt (CPUState *env)
         cause = 0;
         if (env->CP0_Cause & (1 << CP0Ca_IV))
             offset = 0x200;
+
+        if (env->CP0_Config3 & ((1 << CP0C3_VInt) | (1 << CP0C3_VEIC))) {
+            /* Vectored Interrupts.  */
+            unsigned int spacing;
+            unsigned int vector;
+            unsigned int pending = (env->CP0_Cause & CP0Ca_IP_mask) >> 8;
+
+            /* Compute the Vector Spacing.  */
+            spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & ((1 << 6) - 1);
+            spacing <<= 5;
+
+            if (env->CP0_Config3 & (1 << CP0C3_VInt)) {
+                /* For VInt mode, the MIPS computes the vector internally.  */
+                for (vector = 0; vector < 8; vector++) {
+                    if (pending & 1) {
+                        /* Found it.  */
+                        break;
+                    }
+                    pending >>= 1;
+                }
+            } else {
+                /* For VEIC mode, the external interrupt controller feeds the
+                   vector throught the CP0Cause IP lines.  */
+                vector = pending;
+            }
+            offset = 0x200 + vector * spacing;
+        }
         goto set_EPC;
     case EXCP_LTLBL:
         cause = 1;