@@ -136,16 +136,23 @@ static void pci_bios_init_device(u16 bdf)
/* default memory mappings */
for (i = 0; i < PCI_NUM_REGIONS; i++) {
int ofs;
- u32 val, size;
-
+ u32 val, mask, size;
if (i == PCI_ROM_SLOT)
ofs = PCI_ROM_ADDRESS;
else
ofs = PCI_BASE_ADDRESS_0 + i * 4;
- pci_config_writel(bdf, ofs, 0xffffffff);
+
+ val = pci_config_readl(bdf, ofs);
+ if (i == PCI_ROM_SLOT)
+ mask = PCI_ROM_ADDRESS_MASK;
+ else if (val & PCI_BASE_ADDRESS_SPACE_IO)
+ mask = PCI_BASE_ADDRESS_IO_MASK;
+ else
+ mask = PCI_BASE_ADDRESS_MEM_MASK;
+ pci_config_writel(bdf, ofs, val | mask);
val = pci_config_readl(bdf, ofs);
if (val != 0) {
- size = (~(val & ~0xf)) + 1;
+ size = (~(val & mask)) + 1;
if (val & PCI_BASE_ADDRESS_SPACE_IO)
paddr = &pci_bios_io_addr;
else if (size >= 0x04000000)
This cleans up handling of low bits during BAR sizing, to match PCI spec requirements, and to use symbolic constants from pci_regs.h Issues fixed: For ROM BARs, bit 0 is writeable (enable bit), which we not only don't want to set, but it will stick and make us think it's an I/O port resource. Further, PCI spec defines the following bits as reserved: - bit 1 in I/O BAR - bits 10:1 in ROM BAR and we should be careful and preserve any values there, and should ignore anything we read from these registers. Bits 3:2 in I/O BAR might be writeable, so it is wrong to mask them when calculating BAR size. Spec references: See 6.2.5.1 for I/O and memory, and 6.2.5.2 for ROM, 6.1 for reserved bit handling; pages 225, 228 and 214 in PCI spec revision 3.0. See also Qemu pcbios commit 6ddb9f5c742b2b82b1755d7ec2a127f6e20e3806 Original-by: Gleb Natapov <gleb@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> --- So, here's my latest version, I fixed some TABs versus spaces here. Gleb, if you want to rewrite it using 0xffffffff, or go back to your original patch, go ahead. It's not really important, either way. If you are OK as is, let me know and I will try to get this merged.