From patchwork Fri Mar 19 22:55:40 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 49659 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 133EAB7CF6 for ; Thu, 8 Apr 2010 09:02:24 +1000 (EST) Received: from localhost ([127.0.0.1]:57654 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Nze6B-00060i-3z for incoming@patchwork.ozlabs.org; Wed, 07 Apr 2010 18:51:51 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Nze3W-0005JN-Qg for qemu-devel@nongnu.org; Wed, 07 Apr 2010 18:49:06 -0400 Received: from [140.186.70.92] (port=37859 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Nze3R-0005Il-8p for qemu-devel@nongnu.org; Wed, 07 Apr 2010 18:49:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1Nze3P-0003gn-JN for qemu-devel@nongnu.org; Wed, 07 Apr 2010 18:49:00 -0400 Received: from are.twiddle.net ([75.149.56.221]:44514) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1Nze3P-0003gU-7z for qemu-devel@nongnu.org; Wed, 07 Apr 2010 18:48:59 -0400 Received: by are.twiddle.net (Postfix, from userid 5000) id 197FACE6; Wed, 7 Apr 2010 15:48:56 -0700 (PDT) Message-Id: <1611fa9753e511b8e232df1bee135e434890e512.1270680209.git.rth@twiddle.net> In-Reply-To: References: From: Richard Henderson Date: Fri, 19 Mar 2010 15:55:40 -0700 To: qemu-devel@nongnu.org X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) Cc: aurelien@aurel32.net Subject: [Qemu-devel] [PATCH 04/13] target-alpha: Implement cvtql inline. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org It's a simple mask and shift sequence. Also, fix a typo in the actual masks used. Signed-off-by: Richard Henderson --- target-alpha/helper.h | 4 ---- target-alpha/op_helper.c | 20 -------------------- target-alpha/translate.c | 45 +++++++++++++++++++++++++++++++++++++++------ 3 files changed, 39 insertions(+), 30 deletions(-) diff --git a/target-alpha/helper.h b/target-alpha/helper.h index c378195..10c78d0 100644 --- a/target-alpha/helper.h +++ b/target-alpha/helper.h @@ -89,10 +89,6 @@ DEF_HELPER_FLAGS_1(cvttq, TCG_CALL_CONST, i64, i64) DEF_HELPER_FLAGS_1(cvttq_c, TCG_CALL_CONST, i64, i64) DEF_HELPER_FLAGS_1(cvttq_svic, TCG_CALL_CONST, i64, i64) -DEF_HELPER_FLAGS_1(cvtql, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64) -DEF_HELPER_1(cvtql_v, i64, i64) -DEF_HELPER_1(cvtql_sv, i64, i64) - DEF_HELPER_FLAGS_1(setroundmode, TCG_CALL_CONST, void, i32) DEF_HELPER_FLAGS_1(setflushzero, TCG_CALL_CONST, void, i32) DEF_HELPER_FLAGS_0(fp_exc_clear, TCG_CALL_CONST, void) diff --git a/target-alpha/op_helper.c b/target-alpha/op_helper.c index 84867b8..f9cd07a 100644 --- a/target-alpha/op_helper.c +++ b/target-alpha/op_helper.c @@ -1159,26 +1159,6 @@ uint64_t helper_cvtlq (uint64_t a) return (lo & 0x3FFFFFFF) | (hi & 0xc0000000); } -uint64_t helper_cvtql (uint64_t a) -{ - return ((a & 0xC0000000) << 32) | ((a & 0x7FFFFFFF) << 29); -} - -uint64_t helper_cvtql_v (uint64_t a) -{ - if ((int32_t)a != (int64_t)a) - helper_excp(EXCP_ARITH, EXC_M_IOV); - return helper_cvtql(a); -} - -uint64_t helper_cvtql_sv (uint64_t a) -{ - /* ??? I'm pretty sure there's nothing that /sv needs to do that /v - doesn't do. The only thing I can think is that /sv is a valid - instruction merely for completeness in the ISA. */ - return helper_cvtql_v(a); -} - /* PALcode support special instructions */ #if !defined (CONFIG_USER_ONLY) void helper_hw_rei (void) diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 188e76c..44ce830 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -597,6 +597,41 @@ static inline void gen_fp_exc_raise(int rc, int fn11) gen_fp_exc_raise_ignore(rc, fn11, fn11 & QUAL_I ? 0 : float_flag_inexact); } +static void gen_fcvtql(int rb, int rc) +{ + if (unlikely(rc == 31)) { + return; + } + if (unlikely(rb == 31)) { + tcg_gen_movi_i64(cpu_fir[rc], 0); + } else { + TCGv tmp = tcg_temp_new(); + + tcg_gen_andi_i64(tmp, cpu_fir[rb], 0xC0000000); + tcg_gen_andi_i64(cpu_fir[rc], cpu_fir[rb], 0x3FFFFFFF); + tcg_gen_shli_i64(tmp, tmp, 32); + tcg_gen_shli_i64(cpu_fir[rc], cpu_fir[rc], 29); + tcg_gen_or_i64(cpu_fir[rc], cpu_fir[rc], tmp); + + tcg_temp_free(tmp); + } +} + +static void gen_fcvtql_v(DisasContext *ctx, int rb, int rc) +{ + if (rb != 31) { + int lab = gen_new_label(); + TCGv tmp = tcg_temp_new(); + + tcg_gen_ext32s_i64(tmp, cpu_fir[rb]); + tcg_gen_brcond_i64(TCG_COND_EQ, tmp, cpu_fir[rb], lab); + gen_excp(ctx, EXCP_ARITH, EXC_M_IOV); + + gen_set_label(lab); + } + gen_fcvtql(rb, rc); +} + #define FARITH2(name) \ static inline void glue(gen_f, name)(int rb, int rc) \ { \ @@ -612,9 +647,6 @@ static inline void glue(gen_f, name)(int rb, int rc) \ } \ } FARITH2(cvtlq) -FARITH2(cvtql) -FARITH2(cvtql_v) -FARITH2(cvtql_sv) /* ??? VAX instruction qualifiers ignored. */ FARITH2(sqrtf) @@ -2327,11 +2359,12 @@ static inline int translate_one(DisasContext *ctx, uint32_t insn) break; case 0x130: /* CVTQL/V */ - gen_fcvtql_v(rb, rc); - break; case 0x530: /* CVTQL/SV */ - gen_fcvtql_sv(rb, rc); + /* ??? I'm pretty sure there's nothing that /sv needs to do that + /v doesn't do. The only thing I can think is that /sv is a + valid instruction merely for completeness in the ISA. */ + gen_fcvtql_v(ctx, rb, rc); break; default: goto invalid_opc;