[v1,01/12] net: cadence_gem: Disable TSU feature bit

Message ID	1538579266-8389-2-git-send-email-edgar.iglesias@gmail.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Date: Wed, 3 Oct 2018 22:07:35 +0700 Message-Id: <1538579266-8389-2-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1538579266-8389-1-git-send-email-edgar.iglesias@gmail.com> References: <1538579266-8389-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v1 01/12] net: cadence_gem: Disable TSU feature bit Precedence: list Cc: figlesia@xilinx.com, peter.maydell@linaro.org, sstabellini@kernel.org, edgar.iglesias@xilinx.com, sai.pavan.boddu@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, richard.henderson@linaro.org, frederic.konrad@adacore.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	arm: Add first models of Xilinx Versal SoC \| expand [v1,00/12] arm: Add first models of Xilinx Versal SoC [v1,01/12] net: cadence_gem: Disable TSU feature bit [v1,02/12] net: cadence_gem: Announce availability of priority queues [v1,03/12] net: cadence_gem: Use uint32_t for 32bit descriptor words [v1,04/12] net: cadence_gem: Add macro with max number of descriptor words [v1,05/12] net: cadence_gem: Add support for extended descriptors [v1,06/12] net: cadence_gem: Add support for selecting the DMA MemoryRegion [v1,07/12] net: cadence_gem: Implement support for 64bit descriptor addresses [v1,08/12] net: cadence_gem: Announce 64bit addressing support [v1,09/12] target-arm: powerctl: Enable HVC when starting CPUs to EL2 [v1,10/12] target/arm: Add the Cortex-A72 [v1,11/12] hw/arm: versal: Add a model of Xilinx Versal SoC [v1,12/12] hw/arm: versal: Add a virtual Xilinx Versal board

Message ID

1538579266-8389-2-git-send-email-edgar.iglesias@gmail.com

State

New

Headers

From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: qemu-devel@nongnu.org,
	qemu-arm@nongnu.org
Date: Wed,  3 Oct 2018 22:07:35 +0700
Message-Id: <1538579266-8389-2-git-send-email-edgar.iglesias@gmail.com>
In-Reply-To: <1538579266-8389-1-git-send-email-edgar.iglesias@gmail.com>
References: <1538579266-8389-1-git-send-email-edgar.iglesias@gmail.com>
Subject: [Qemu-devel] [PATCH v1 01/12] net: cadence_gem: Disable TSU feature
	bit
Precedence: list
Cc: figlesia@xilinx.com, peter.maydell@linaro.org, sstabellini@kernel.org,
	edgar.iglesias@xilinx.com, sai.pavan.boddu@xilinx.com,
	frasse.iglesias@gmail.com, alistair@alistair23.me,
	richard.henderson@linaro.org, frederic.konrad@adacore.com
Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Sender: "Qemu-devel"
	<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>

Series

arm: Add first models of Xilinx Versal SoC | expand

Commit Message

Edgar E. Iglesias Oct. 3, 2018, 3:07 p.m. UTC

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Disable the Timestamping Unit feature bit since QEMU does not
yet support it. This allows guest SW to correctly probe for
its existance.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 hw/net/cadence_gem.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Alistair Francis Oct. 4, 2018, 5:36 p.m. UTC | #1

On Wed, Oct 3, 2018 at 8:11 AM Edgar E. Iglesias
<edgar.iglesias@gmail.com> wrote:
>
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Disable the Timestamping Unit feature bit since QEMU does not
> yet support it. This allows guest SW to correctly probe for
> its existance.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  hw/net/cadence_gem.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
> index 0fa4b0d..e560b7a 100644
> --- a/hw/net/cadence_gem.c
> +++ b/hw/net/cadence_gem.c
> @@ -1228,7 +1228,7 @@ static void gem_reset(DeviceState *d)
>      s->regs[GEM_MODID] = s->revision;
>      s->regs[GEM_DESCONF] = 0x02500111;
>      s->regs[GEM_DESCONF2] = 0x2ab13fff;
> -    s->regs[GEM_DESCONF5] = 0x002f2145;
> +    s->regs[GEM_DESCONF5] = 0x002f2045;
>      s->regs[GEM_DESCONF6] = 0x00000200;
>
>      /* Set MAC address */
> --
> 2.7.4
>
>

diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 0fa4b0d..e560b7a 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -1228,7 +1228,7 @@  static void gem_reset(DeviceState *d)
     s->regs[GEM_MODID] = s->revision;
     s->regs[GEM_DESCONF] = 0x02500111;
     s->regs[GEM_DESCONF2] = 0x2ab13fff;
-    s->regs[GEM_DESCONF5] = 0x002f2145;
+    s->regs[GEM_DESCONF5] = 0x002f2045;
     s->regs[GEM_DESCONF6] = 0x00000200;
 
     /* Set MAC address */

[v1,01/12] net: cadence_gem: Disable TSU feature bit

Commit Message

Comments

Patch