From patchwork Fri Jul 29 09:11:12 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leon Alrae X-Patchwork-Id: 654051 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3s133R0ssnz9t0X for ; Fri, 29 Jul 2016 19:15:15 +1000 (AEST) Received: from localhost ([::1]:58343 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bT3sv-0001RP-6p for incoming@patchwork.ozlabs.org; Fri, 29 Jul 2016 05:15:13 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40362) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bT3pj-0007Ah-VC for qemu-devel@nongnu.org; Fri, 29 Jul 2016 05:11:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bT3pe-0003yo-KI for qemu-devel@nongnu.org; Fri, 29 Jul 2016 05:11:55 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:17708) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bT3pe-0003yg-EM for qemu-devel@nongnu.org; Fri, 29 Jul 2016 05:11:50 -0400 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Forcepoint Email with ESMTPS id 017066E94EAD1 for ; Fri, 29 Jul 2016 10:11:37 +0100 (IST) Received: from hhmipssw204.hh.imgtec.org (10.100.21.121) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.294.0; Fri, 29 Jul 2016 10:11:39 +0100 From: Leon Alrae To: Date: Fri, 29 Jul 2016 10:11:12 +0100 Message-ID: <1469783472-18639-3-git-send-email-leon.alrae@imgtec.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1469783472-18639-1-git-send-email-leon.alrae@imgtec.com> References: <1469783472-18639-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [10.100.21.121] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Subject: [Qemu-devel] [PULL 2/2] target-mips: fix EntryHi.EHINV being cleared on TLB exception X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" While implementing TLB invalidation feature we forgot to modify part of code responsible for updating EntryHi during TLB exception. Consequently EntryHi.EHINV is unexpectedly cleared on the exception. Signed-off-by: Leon Alrae --- target-mips/helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target-mips/helper.c b/target-mips/helper.c index 9fbca26..c864b15 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -396,6 +396,7 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, env->CP0_Context = (env->CP0_Context & ~0x007fffff) | ((address >> 9) & 0x007ffff0); env->CP0_EntryHi = (env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask) | + (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) | (address & (TARGET_PAGE_MASK << 1)); #if defined(TARGET_MIPS64) env->CP0_EntryHi &= env->SEGMask;