From patchwork Tue Jul 12 11:14:50 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leon Alrae X-Patchwork-Id: 647337 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3rpfgQ3Vy6z9sCt for ; Tue, 12 Jul 2016 21:21:54 +1000 (AEST) Received: from localhost ([::1]:39056 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bMvlA-0003rI-C1 for incoming@patchwork.ozlabs.org; Tue, 12 Jul 2016 07:21:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47891) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bMvfE-0005kh-PF for qemu-devel@nongnu.org; Tue, 12 Jul 2016 07:15:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bMvfD-000224-G5 for qemu-devel@nongnu.org; Tue, 12 Jul 2016 07:15:44 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:32818) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bMvfD-00021x-9f for qemu-devel@nongnu.org; Tue, 12 Jul 2016 07:15:43 -0400 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Forcepoint Email with ESMTPS id D820293CD616D for ; Tue, 12 Jul 2016 12:15:28 +0100 (IST) Received: from hhmipssw204.hh.imgtec.org (10.100.21.121) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.294.0; Tue, 12 Jul 2016 12:15:31 +0100 From: Leon Alrae To: Date: Tue, 12 Jul 2016 12:14:50 +0100 Message-ID: <1468322097-2315-5-git-send-email-leon.alrae@imgtec.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1468322097-2315-1-git-send-email-leon.alrae@imgtec.com> References: <1468322097-2315-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [10.100.21.121] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Subject: [Qemu-devel] [PULL 04/11] target-mips: add exception base to MIPS CPU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Replace hardcoded 0xbfc00000 with exception_base which is initialized with this default address so there is no functional change here. However, it is now exposed and consequently it will be possible to modify it from outside of the CPU. Signed-off-by: Leon Alrae --- target-mips/cpu.h | 2 ++ target-mips/helper.c | 6 +++--- target-mips/translate.c | 9 ++++++++- 3 files changed, 13 insertions(+), 4 deletions(-) diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 1037f9b..fe1c4b8 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -616,6 +616,7 @@ struct CPUMIPSState { void *irq[8]; QEMUTimer *timer; /* Internal timer */ MemoryRegion *itc_tag; /* ITC Configuration Tags */ + target_ulong exception_base; /* ExceptionBase input to the core */ }; /** @@ -807,6 +808,7 @@ int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); #define cpu_init(cpu_model) CPU(cpu_mips_init(cpu_model)) bool cpu_supports_cps_smp(const char *cpu_model); +void cpu_set_exception_base(int vp_index, target_ulong address); /* TODO QOM'ify CPU reset and remove */ void cpu_state_reset(CPUMIPSState *s); diff --git a/target-mips/helper.c b/target-mips/helper.c index 65fbef0..1402ff0 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -640,7 +640,7 @@ void mips_cpu_do_interrupt(CPUState *cs) /* EJTAG probe trap enable is not implemented... */ if (!(env->CP0_Status & (1 << CP0St_EXL))) env->CP0_Cause &= ~(1U << CP0Ca_BD); - env->active_tc.PC = (int32_t)0xBFC00480; + env->active_tc.PC = env->exception_base + 0x480; set_hflags_for_handler(env); break; case EXCP_RESET: @@ -667,7 +667,7 @@ void mips_cpu_do_interrupt(CPUState *cs) env->hflags &= ~(MIPS_HFLAG_KSU); if (!(env->CP0_Status & (1 << CP0St_EXL))) env->CP0_Cause &= ~(1U << CP0Ca_BD); - env->active_tc.PC = (int32_t)0xBFC00000; + env->active_tc.PC = env->exception_base; set_hflags_for_handler(env); break; case EXCP_EXT_INTERRUPT: @@ -849,7 +849,7 @@ void mips_cpu_do_interrupt(CPUState *cs) } env->hflags &= ~MIPS_HFLAG_BMASK; if (env->CP0_Status & (1 << CP0St_BEV)) { - env->active_tc.PC = (int32_t)0xBFC00200; + env->active_tc.PC = env->exception_base + 0x200; } else { env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff); } diff --git a/target-mips/translate.c b/target-mips/translate.c index cc321e9..c302fa3 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -20169,6 +20169,7 @@ MIPSCPU *cpu_mips_init(const char *cpu_model) cpu = MIPS_CPU(object_new(TYPE_MIPS_CPU)); env = &cpu->env; env->cpu_model = def; + env->exception_base = (int32_t)0xBFC00000; #ifndef CONFIG_USER_ONLY mmu_init(env, def); @@ -20191,6 +20192,12 @@ bool cpu_supports_cps_smp(const char *cpu_model) return (def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0; } +void cpu_set_exception_base(int vp_index, target_ulong address) +{ + MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index)); + vp->env.exception_base = address; +} + void cpu_state_reset(CPUMIPSState *env) { MIPSCPU *cpu = mips_env_get_cpu(env); @@ -20281,7 +20288,7 @@ void cpu_state_reset(CPUMIPSState *env) } else { env->CP0_ErrorEPC = env->active_tc.PC; } - env->active_tc.PC = (int32_t)0xBFC00000; + env->active_tc.PC = env->exception_base; env->CP0_Random = env->tlb->nb_tlb - 1; env->tlb->tlb_in_use = env->tlb->nb_tlb; env->CP0_Wired = 0;