From patchwork Mon Jun 27 15:19:12 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leon Alrae X-Patchwork-Id: 641107 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3rdXrp0DPzz9sBG for ; Tue, 28 Jun 2016 01:28:26 +1000 (AEST) Received: from localhost ([::1]:59346 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bHYSV-0003GB-Nv for incoming@patchwork.ozlabs.org; Mon, 27 Jun 2016 11:28:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47463) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bHYJx-0001oQ-6g for qemu-devel@nongnu.org; Mon, 27 Jun 2016 11:19:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bHYJv-0001H4-9v for qemu-devel@nongnu.org; Mon, 27 Jun 2016 11:19:32 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:36140) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bHYJv-0001Gn-48 for qemu-devel@nongnu.org; Mon, 27 Jun 2016 11:19:31 -0400 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Forcepoint Email with ESMTPS id B4B6FD815E8A4; Mon, 27 Jun 2016 16:19:26 +0100 (IST) Received: from hhmipssw204.hh.imgtec.org (10.100.21.121) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.294.0; Mon, 27 Jun 2016 16:19:29 +0100 From: Leon Alrae To: Date: Mon, 27 Jun 2016 16:19:12 +0100 Message-ID: <1467040752-18666-5-git-send-email-leon.alrae@imgtec.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1467040752-18666-1-git-send-email-leon.alrae@imgtec.com> References: <1467040752-18666-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [10.100.21.121] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Subject: [Qemu-devel] [PATCH 4/4] target-mips: enable 10-bit ASIDs in I6400 CPU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Leon Alrae --- target-mips/translate_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index c43bdb7..39ed5c4 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -685,7 +685,7 @@ static const mips_def_t mips_defs[] = (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt), .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) | - (0xfc << CP0C4_KScrExist), + (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist), .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) | (1 << CP0C5_LLB) | (1 << CP0C5_MRP), .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |