From patchwork Wed Apr 27 22:21:06 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Hogan X-Patchwork-Id: 615853 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3qwDwG4L1qz9sBX for ; Thu, 28 Apr 2016 08:22:04 +1000 (AEST) Received: from localhost ([::1]:45651 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1avXqL-0008Lu-9u for incoming@patchwork.ozlabs.org; Wed, 27 Apr 2016 18:22:01 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59791) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1avXq1-0007l9-2N for qemu-devel@nongnu.org; Wed, 27 Apr 2016 18:21:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1avXpx-0006pP-2I for qemu-devel@nongnu.org; Wed, 27 Apr 2016 18:21:41 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:22047) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1avXpw-0006p8-Sb for qemu-devel@nongnu.org; Wed, 27 Apr 2016 18:21:36 -0400 Received: from HHMAIL01.hh.imgtec.org (unknown [10.100.10.19]) by Websense Email with ESMTPS id E81253B2405BD; Wed, 27 Apr 2016 23:21:27 +0100 (IST) Received: from LEMAIL01.le.imgtec.org (192.168.152.62) by HHMAIL01.hh.imgtec.org (10.100.10.19) with Microsoft SMTP Server (TLS) id 14.3.266.1; Wed, 27 Apr 2016 23:21:32 +0100 Received: from jhogan-linux.le.imgtec.org (192.168.154.110) by LEMAIL01.le.imgtec.org (192.168.152.62) with Microsoft SMTP Server (TLS) id 14.3.266.1; Wed, 27 Apr 2016 23:21:32 +0100 From: James Hogan To: Date: Wed, 27 Apr 2016 23:21:06 +0100 Message-ID: <1461795666-4704-1-git-send-email-james.hogan@imgtec.com> X-Mailer: git-send-email 2.4.10 MIME-Version: 1.0 X-Originating-IP: [192.168.154.110] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Subject: [Qemu-devel] [PATCH] target-mips: Fix RDHWR exception host PC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yongbok Kim , James Hogan , Leon Alrae , Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Commit b00c72180c36 ("target-mips: add PC, XNP reg numbers to RDHWR") changed the rdhwr helpers to use check_hwrena() to check the register being accessed is enabled in CP0_HWREna when used from user mode. If that check fails an EXCP_RI exception is raised at the host PC calculated with GETPC(). However check_hwrena() may not be fully inlined as the do_raise_exception() part of it is common regardless of the arguments. This causes GETPC() to calculate the address in the call in the helper instead of the generated code calling the helper. No TB will be found and the EPC reported with the resulting guest RI exception points to the beginning of the TB instead of the RDHWR instruction. We can't reliably force check_hwrena() to be inlined, and converting it to a macro would be ugly, so instead pass the host PC in as an argument, with each rdhwr helper passing GETPC(). This should avoid any dependence on compiler behaviour, and in practice seems to prevent the partial inlining of check_hwrena() on x86_64. This issue causes failures when running a MIPS KVM (trap & emulate) guest in a MIPS QEMU TCG guest, as the inner guest kernel will do a RDHWR of counter, which is disabled in the outer guest's CP0_HWREna by KVM so it can emulate the inner guest's counter. The emulation fails and the RI exception is passed to the inner guest. Fixes: b00c72180c36 ("target-mips: add PC, XNP reg numbers to RDHWR") Signed-off-by: James Hogan Cc: Leon Alrae Cc: Yongbok Kim Cc: Aurelien Jarno Reviewed-by: Aurelien Jarno --- target-mips/op_helper.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index 8ec1bef7d034..4417e6ba225f 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -2294,29 +2294,29 @@ void helper_deret(CPUMIPSState *env) } #endif /* !CONFIG_USER_ONLY */ -static inline void check_hwrena(CPUMIPSState *env, int reg) +static inline void check_hwrena(CPUMIPSState *env, int reg, uintptr_t pc) { if ((env->hflags & MIPS_HFLAG_CP0) || (env->CP0_HWREna & (1 << reg))) { return; } - do_raise_exception(env, EXCP_RI, GETPC()); + do_raise_exception(env, EXCP_RI, pc); } target_ulong helper_rdhwr_cpunum(CPUMIPSState *env) { - check_hwrena(env, 0); + check_hwrena(env, 0, GETPC()); return env->CP0_EBase & 0x3ff; } target_ulong helper_rdhwr_synci_step(CPUMIPSState *env) { - check_hwrena(env, 1); + check_hwrena(env, 1, GETPC()); return env->SYNCI_Step; } target_ulong helper_rdhwr_cc(CPUMIPSState *env) { - check_hwrena(env, 2); + check_hwrena(env, 2, GETPC()); #ifdef CONFIG_USER_ONLY return env->CP0_Count; #else @@ -2326,19 +2326,19 @@ target_ulong helper_rdhwr_cc(CPUMIPSState *env) target_ulong helper_rdhwr_ccres(CPUMIPSState *env) { - check_hwrena(env, 3); + check_hwrena(env, 3, GETPC()); return env->CCRes; } target_ulong helper_rdhwr_performance(CPUMIPSState *env) { - check_hwrena(env, 4); + check_hwrena(env, 4, GETPC()); return env->CP0_Performance0; } target_ulong helper_rdhwr_xnp(CPUMIPSState *env) { - check_hwrena(env, 5); + check_hwrena(env, 5, GETPC()); return (env->CP0_Config5 >> CP0C5_XNP) & 1; }