From patchwork Fri Apr 1 14:49:39 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Hogan X-Patchwork-Id: 604859 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3qc4BL301yz9sdm for ; Sat, 2 Apr 2016 01:53:14 +1100 (AEDT) Received: from localhost ([::1]:44856 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1am0Rk-0000mq-IU for incoming@patchwork.ozlabs.org; Fri, 01 Apr 2016 10:53:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51379) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1am0Qw-00086v-5U for qemu-devel@nongnu.org; Fri, 01 Apr 2016 10:52:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1am0Qr-0006i1-UM for qemu-devel@nongnu.org; Fri, 01 Apr 2016 10:52:22 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:64253) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1am0Qr-0006hx-P3 for qemu-devel@nongnu.org; Fri, 01 Apr 2016 10:52:17 -0400 Received: from HHMAIL01.hh.imgtec.org (unknown [10.100.10.19]) by Websense Email Security Gateway with ESMTPS id D2D2FC165A495; Fri, 1 Apr 2016 15:52:13 +0100 (IST) Received: from LEMAIL01.le.imgtec.org (192.168.152.62) by HHMAIL01.hh.imgtec.org (10.100.10.19) with Microsoft SMTP Server (TLS) id 14.3.266.1; Fri, 1 Apr 2016 15:52:16 +0100 Received: from jhogan-linux.le.imgtec.org (192.168.154.110) by LEMAIL01.le.imgtec.org (192.168.152.62) with Microsoft SMTP Server (TLS) id 14.3.266.1; Fri, 1 Apr 2016 15:52:15 +0100 From: James Hogan To: Date: Fri, 1 Apr 2016 15:49:39 +0100 Message-ID: <1459522179-6584-1-git-send-email-james.hogan@imgtec.com> X-Mailer: git-send-email 2.4.10 MIME-Version: 1.0 X-Originating-IP: [192.168.154.110] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Cc: James Hogan , Aurelien Jarno , Richard Henderson Subject: [Qemu-devel] [PATCH] tcg/mips: Fix type of tcg_target_reg_alloc_order[] X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The MIPS TCG backend is the only one to have tcg_target_reg_alloc_order[] elements of type TCGReg rather than int. This resulted in commit 91478cefaaf2 ("tcg: Allocate indirect_base temporaries in a different order") breaking the build on MIPS since the type differed from indirect_reg_alloc_order[]: tcg/tcg.c:1725:44: error: pointer type mismatch in conditional expression [-Werror] order = rev ? indirect_reg_alloc_order : tcg_target_reg_alloc_order; ^ Make it an array of ints to fix the build and match other architectures. Fixes: 91478cefaaf2 ("tcg: Allocate indirect_base temporaries in a different order") Signed-off-by: James Hogan Cc: Aurelien Jarno Cc: Richard Henderson Reviewed-by: Richard Henderson Acked-by: Aurelien Jarno --- tcg/mips/tcg-target.inc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c index 297bd00910b7..682e19897db0 100644 --- a/tcg/mips/tcg-target.inc.c +++ b/tcg/mips/tcg-target.inc.c @@ -76,7 +76,7 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { #define TCG_TMP1 TCG_REG_T9 /* check if we really need so many registers :P */ -static const TCGReg tcg_target_reg_alloc_order[] = { +static const int tcg_target_reg_alloc_order[] = { /* Call saved registers. */ TCG_REG_S0, TCG_REG_S1,