From patchwork Tue Mar 29 09:57:03 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leon Alrae X-Patchwork-Id: 602805 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3qZ5p20yp2z9s5g for ; Tue, 29 Mar 2016 20:58:50 +1100 (AEDT) Received: from localhost ([::1]:45493 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1akqQC-00065i-DK for incoming@patchwork.ozlabs.org; Tue, 29 Mar 2016 05:58:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53129) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1akqPa-0004te-Cf for qemu-devel@nongnu.org; Tue, 29 Mar 2016 05:58:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1akqPZ-0007yq-8x for qemu-devel@nongnu.org; Tue, 29 Mar 2016 05:58:10 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:4683) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1akqPZ-0007yS-1d for qemu-devel@nongnu.org; Tue, 29 Mar 2016 05:58:09 -0400 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Websense Email Security Gateway with ESMTPS id 5B1314506EDA3 for ; Tue, 29 Mar 2016 10:58:05 +0100 (IST) Received: from lalrae-linux.kl.imgtec.org (192.168.169.37) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.266.1; Tue, 29 Mar 2016 10:58:07 +0100 From: Leon Alrae To: Date: Tue, 29 Mar 2016 10:57:03 +0100 Message-ID: <1459245425-4374-20-git-send-email-leon.alrae@imgtec.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1459245425-4374-1-git-send-email-leon.alrae@imgtec.com> References: <1459245425-4374-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.169.37] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Subject: [Qemu-devel] [PULL 19/21] hw/mips/cps: enable ITU for multithreading processors X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Make ITU available in the system if CPU supports multithreading and is part of CPS. Signed-off-by: Leon Alrae --- hw/mips/cps.c | 32 ++++++++++++++++++++++++++++++++ include/hw/mips/cps.h | 2 ++ 2 files changed, 34 insertions(+) diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 59e7926..d2ee0e4 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -21,6 +21,7 @@ #include "hw/mips/cps.h" #include "hw/mips/mips.h" #include "hw/mips/cpudevs.h" +#include "sysemu/kvm.h" qemu_irq get_cps_irq(MIPSCPSState *s, int pin_number) { @@ -55,6 +56,14 @@ static void main_cpu_reset(void *opaque) cs->halted = 1; } +static bool cpu_mips_itu_supported(CPUMIPSState *env) +{ + bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) || + (env->CP0_Config3 & (1 << CP0C3_MT)); + + return is_mt && !kvm_enabled(); +} + static void mips_cps_realize(DeviceState *dev, Error **errp) { MIPSCPSState *s = MIPS_CPS(dev); @@ -63,6 +72,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) int i; Error *err = NULL; target_ulong gcr_base; + bool itu_present = false; for (i = 0; i < s->num_vp; i++) { cpu = cpu_mips_init(s->cpu_model); @@ -75,12 +85,34 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) /* Init internal devices */ cpu_mips_irq_init_cpu(env); cpu_mips_clock_init(env); + if (cpu_mips_itu_supported(env)) { + itu_present = true; + /* Attach ITC Tag to the VP */ + env->itc_tag = mips_itu_get_tag_region(&s->itu); + } qemu_register_reset(main_cpu_reset, cpu); } cpu = MIPS_CPU(first_cpu); env = &cpu->env; + /* Inter-Thread Communication Unit */ + if (itu_present) { + object_initialize(&s->itu, sizeof(s->itu), TYPE_MIPS_ITU); + qdev_set_parent_bus(DEVICE(&s->itu), sysbus_get_default()); + + object_property_set_int(OBJECT(&s->itu), 16, "num-fifo", &err); + object_property_set_int(OBJECT(&s->itu), 16, "num-semaphores", &err); + object_property_set_bool(OBJECT(&s->itu), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + + memory_region_add_subregion(&s->container, 0, + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->itu), 0)); + } + /* Cluster Power Controller */ object_initialize(&s->cpc, sizeof(s->cpc), TYPE_MIPS_CPC); qdev_set_parent_bus(DEVICE(&s->cpc), sysbus_get_default()); diff --git a/include/hw/mips/cps.h b/include/hw/mips/cps.h index 88be765..4dbae9c 100644 --- a/include/hw/mips/cps.h +++ b/include/hw/mips/cps.h @@ -23,6 +23,7 @@ #include "hw/sysbus.h" #include "hw/misc/mips_cmgcr.h" #include "hw/misc/mips_cpc.h" +#include "hw/misc/mips_itu.h" #define TYPE_MIPS_CPS "mips-cps" #define MIPS_CPS(obj) OBJECT_CHECK(MIPSCPSState, (obj), TYPE_MIPS_CPS) @@ -37,6 +38,7 @@ typedef struct MIPSCPSState { MemoryRegion container; MIPSGCRState gcr; MIPSCPCState cpc; + MIPSITUState itu; } MIPSCPSState; qemu_irq get_cps_irq(MIPSCPSState *cps, int pin_number);