From patchwork Tue Mar 15 09:59:29 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leon Alrae X-Patchwork-Id: 597421 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3qPVWQ544Sz9sds for ; Tue, 15 Mar 2016 21:01:22 +1100 (AEDT) Received: from localhost ([::1]:46913 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aflmx-0003FJ-PR for incoming@patchwork.ozlabs.org; Tue, 15 Mar 2016 06:01:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51299) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aflmA-0001vR-AL for qemu-devel@nongnu.org; Tue, 15 Mar 2016 06:00:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aflm6-0007oG-D8 for qemu-devel@nongnu.org; Tue, 15 Mar 2016 06:00:30 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:11247) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aflm5-0007o7-TI for qemu-devel@nongnu.org; Tue, 15 Mar 2016 06:00:26 -0400 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Websense Email Security Gateway with ESMTPS id DA61F372DABBD; Tue, 15 Mar 2016 10:00:22 +0000 (GMT) Received: from lalrae-linux.kl.imgtec.org (192.168.169.37) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.266.1; Tue, 15 Mar 2016 10:00:24 +0000 From: Leon Alrae To: Date: Tue, 15 Mar 2016 09:59:29 +0000 Message-ID: <1458035976-23414-5-git-send-email-leon.alrae@imgtec.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1458035976-23414-1-git-send-email-leon.alrae@imgtec.com> References: <1458035976-23414-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.169.37] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Cc: yongbok.kim@imgtec.com, peter.maydell@linaro.org, james.hogan@imgtec.com, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH v2 04/11] hw/mips/cps: create GCR block inside CPS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Leon Alrae --- hw/mips/cps.c | 23 +++++++++++++++++++++++ include/hw/mips/cps.h | 2 ++ 2 files changed, 25 insertions(+) diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 782aa2b..cfd808d 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -61,6 +61,8 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) CPUMIPSState *env; MIPSCPU *cpu; int i; + Error *err = NULL; + target_ulong gcr_base; for (i = 0; i < s->num_vp; i++) { cpu = cpu_mips_init(s->cpu_model); @@ -75,6 +77,27 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) cpu_mips_clock_init(env); qemu_register_reset(main_cpu_reset, cpu); } + + cpu = MIPS_CPU(first_cpu); + env = &cpu->env; + + /* Global Configuration Registers */ + gcr_base = env->CP0_CMGCRBase << 4; + + object_initialize(&s->gcr, sizeof(s->gcr), TYPE_MIPS_GCR); + qdev_set_parent_bus(DEVICE(&s->gcr), sysbus_get_default()); + + object_property_set_int(OBJECT(&s->gcr), s->num_vp, "num-vp", &err); + object_property_set_int(OBJECT(&s->gcr), 0x800, "gcr-rev", &err); + object_property_set_int(OBJECT(&s->gcr), gcr_base, "gcr-base", &err); + object_property_set_bool(OBJECT(&s->gcr), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + + memory_region_add_subregion(&s->container, gcr_base, + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gcr), 0)); } static Property mips_cps_properties[] = { diff --git a/include/hw/mips/cps.h b/include/hw/mips/cps.h index fb3528a..1b200d6 100644 --- a/include/hw/mips/cps.h +++ b/include/hw/mips/cps.h @@ -21,6 +21,7 @@ #define MIPS_CPS_H #include "hw/sysbus.h" +#include "hw/misc/mips_cmgcr.h" #define TYPE_MIPS_CPS "mips-cps" #define MIPS_CPS(obj) OBJECT_CHECK(MIPSCPSState, (obj), TYPE_MIPS_CPS) @@ -33,6 +34,7 @@ typedef struct MIPSCPSState { char *cpu_model; MemoryRegion container; + MIPSGCRState gcr; } MIPSCPSState; qemu_irq get_cps_irq(MIPSCPSState *cps, int pin_number);