From patchwork Fri Feb 26 16:19:58 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leon Alrae X-Patchwork-Id: 589172 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4C7E714029E for ; Sat, 27 Feb 2016 03:21:15 +1100 (AEDT) Received: from localhost ([::1]:50895 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aZL8j-0002c9-9Y for incoming@patchwork.ozlabs.org; Fri, 26 Feb 2016 11:21:13 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40275) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aZL8C-0001sW-E1 for qemu-devel@nongnu.org; Fri, 26 Feb 2016 11:20:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aZL8B-0003fb-10 for qemu-devel@nongnu.org; Fri, 26 Feb 2016 11:20:40 -0500 Received: from mailapp01.imgtec.com ([195.59.15.196]:25633) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aZL8A-0003f2-Bi for qemu-devel@nongnu.org; Fri, 26 Feb 2016 11:20:38 -0500 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Websense Email Security Gateway with ESMTPS id 55E79B1501904; Fri, 26 Feb 2016 16:20:34 +0000 (GMT) Received: from lalrae-linux.kl.imgtec.org (192.168.169.37) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.266.1; Fri, 26 Feb 2016 16:20:37 +0000 From: Leon Alrae To: Date: Fri, 26 Feb 2016 16:19:58 +0000 Message-ID: <1456503598-27824-3-git-send-email-leon.alrae@imgtec.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1456503598-27824-1-git-send-email-leon.alrae@imgtec.com> References: <1456503598-27824-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.169.37] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Cc: aurelien@aurel32.net Subject: [Qemu-devel] [PATCH 2/2] hw/mips_malta: add CPC to the Malta board X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org On Malta, after reset, only VP0 on Core0 starts the execution. Other VPs are halted until VP0 powers them up using Cluster Power Controller. Signed-off-by: Leon Alrae --- hw/mips/mips_malta.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index 1fb17fb..34cc4cb 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -57,6 +57,7 @@ #include "exec/semihost.h" #include "hw/misc/mips_gcr.h" #include "hw/intc/mips_gic.h" +#include "hw/misc/mips_cpc.h" //#define DEBUG_BOARD_INIT @@ -97,6 +98,7 @@ typedef struct { MIPSGCRState gcr; MIPSGICState gic; + MIPSCPCState cpc; qemu_irq *i8259; } MaltaState; @@ -617,6 +619,19 @@ static void gic_init(MaltaState *s, Error **err) sysbus_mmio_map(gicbusdev, 0, gicbase); } +static void cpc_init(MaltaState *s, Error **err) +{ + object_initialize(&s->cpc, sizeof(s->cpc), TYPE_MIPS_CPC); + qdev_set_parent_bus(DEVICE(&s->cpc), sysbus_get_default()); + + object_property_set_bool(OBJECT(&s->cpc), true, "realized", err); + if (*err != NULL) { + return; + } + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpc), 0, CPC_BASE_ADDR); +} + /* Network support */ static void network_init(PCIBus *pci_bus) { @@ -937,6 +952,7 @@ static void malta_mips_config(MIPSCPU *cpu) static void main_cpu_reset(void *opaque) { MIPSCPU *cpu = opaque; + CPUState *cs = CPU(cpu); CPUMIPSState *env = &cpu->env; cpu_reset(CPU(cpu)); @@ -954,6 +970,15 @@ static void main_cpu_reset(void *opaque) /* Start running from the bootloader we wrote to end of RAM */ env->active_tc.PC = 0x40000000 + loaderparams.ram_low_size; } + + /* At reset only VP0 on Core0 will start executing the code, other + VPs are halted until VP0 powers them up through Cluster Power + Controller. */ + if ((env->CP0_Config5 & (1 << CP0C5_VP)) && + (env->CP0_Config3 & (1 << CP0C3_CMGCR)) && + (cs->cpu_index != 0)) { + cs->halted = 1; + } } static @@ -1200,6 +1225,11 @@ void mips_malta_init(MachineState *machine) error_report("%s", error_get_pretty(err)); exit(1); } + cpc_init(s, &err); + if (err != NULL) { + error_report("%s", error_get_pretty(err)); + exit(1); + } } /*