From patchwork Fri Oct 30 15:00:51 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leon Alrae X-Patchwork-Id: 538376 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id C539A140D92 for ; Sat, 31 Oct 2015 02:05:07 +1100 (AEDT) Received: from localhost ([::1]:51135 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZsBEn-0006I1-Dg for incoming@patchwork.ozlabs.org; Fri, 30 Oct 2015 11:05:05 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42439) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZsBBQ-0008Lk-El for qemu-devel@nongnu.org; Fri, 30 Oct 2015 11:01:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZsBBN-0001oO-GO for qemu-devel@nongnu.org; Fri, 30 Oct 2015 11:01:36 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:40836) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZsBBN-0001o8-BI for qemu-devel@nongnu.org; Fri, 30 Oct 2015 11:01:33 -0400 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Websense Email Security Gateway with ESMTPS id 0F18F90EFC4D1 for ; Fri, 30 Oct 2015 15:01:30 +0000 (GMT) Received: from lalrae-linux.kl.imgtec.org (192.168.14.163) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.235.1; Fri, 30 Oct 2015 15:01:32 +0000 From: Leon Alrae To: Date: Fri, 30 Oct 2015 15:00:51 +0000 Message-ID: <1446217252-3637-9-git-send-email-leon.alrae@imgtec.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1446217252-3637-1-git-send-email-leon.alrae@imgtec.com> References: <1446217252-3637-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.14.163] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Cc: Yongbok Kim Subject: [Qemu-devel] [PULL 8/9] target-mips: add SIGRIE instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Yongbok Kim Add SIGRIE (Signal Reserved Instruction Exception) for both MIPS and microMIPS. The instruction allows to use the 16-bit code field for software use. This instruction is introduced by and required as of Release 6. Signed-off-by: Yongbok Kim Reviewed-by: Leon Alrae Signed-off-by: Leon Alrae --- target-mips/translate.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index bacac2b..5626647 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -323,6 +323,7 @@ enum { OPC_TLTIU = (0x0B << 16) | OPC_REGIMM, OPC_TEQI = (0x0C << 16) | OPC_REGIMM, OPC_TNEI = (0x0E << 16) | OPC_REGIMM, + OPC_SIGRIE = (0x17 << 16) | OPC_REGIMM, OPC_SYNCI = (0x1F << 16) | OPC_REGIMM, OPC_DAHI = (0x06 << 16) | OPC_REGIMM, @@ -12031,7 +12032,8 @@ enum { LSA = 0x0f, ALIGN = 0x1f, EXT = 0x2c, - POOL32AXF = 0x3c + POOL32AXF = 0x3c, + SIGRIE = 0x3f }; /* POOL32AXF encoding of minor opcode field extension */ @@ -13655,6 +13657,10 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) case BREAK32: generate_exception_end(ctx, EXCP_BREAK); break; + case SIGRIE: + check_insn(ctx, ISA_MIPS32R6); + generate_exception_end(ctx, EXCP_RI); + break; default: pool32a_invalid: MIPS_INVAL("pool32a"); @@ -18973,6 +18979,10 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) check_insn_opc_removed(ctx, ISA_MIPS32R6); gen_trap(ctx, op1, rs, -1, imm); break; + case OPC_SIGRIE: + check_insn(ctx, ISA_MIPS32R6); + generate_exception_end(ctx, EXCP_RI); + break; case OPC_SYNCI: check_insn(ctx, ISA_MIPS32R2); /* Break the TB to be able to sync copied instructions