From patchwork Fri Oct 30 15:00:46 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leon Alrae X-Patchwork-Id: 538377 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id B7E5A140D92 for ; Sat, 31 Oct 2015 02:05:18 +1100 (AEDT) Received: from localhost ([::1]:51141 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZsBEy-0006ct-8p for incoming@patchwork.ozlabs.org; Fri, 30 Oct 2015 11:05:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42453) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZsBBR-0008MG-0I for qemu-devel@nongnu.org; Fri, 30 Oct 2015 11:01:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZsBBL-0001nO-4B for qemu-devel@nongnu.org; Fri, 30 Oct 2015 11:01:36 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:26596) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZsBBK-0001nJ-Uu for qemu-devel@nongnu.org; Fri, 30 Oct 2015 11:01:31 -0400 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Websense Email Security Gateway with ESMTPS id 2858AE5DA509B for ; Fri, 30 Oct 2015 15:01:27 +0000 (GMT) Received: from lalrae-linux.kl.imgtec.org (192.168.14.163) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.235.1; Fri, 30 Oct 2015 15:01:29 +0000 From: Leon Alrae To: Date: Fri, 30 Oct 2015 15:00:46 +0000 Message-ID: <1446217252-3637-4-git-send-email-leon.alrae@imgtec.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1446217252-3637-1-git-send-email-leon.alrae@imgtec.com> References: <1446217252-3637-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.14.163] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Subject: [Qemu-devel] [PULL 3/9] target-mips: update writing to CP0.Status.KX/SX/UX in MIPS Release R6 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Implement the relationship between CP0.Status.KX, SX and UX. It should not be possible to set UX bit if SX is 0, the same applies for setting SX if KX is 0. Signed-off-by: Leon Alrae --- target-mips/cpu.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 3799d26..c68681d 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -1001,7 +1001,12 @@ static inline void cpu_mips_store_status(CPUMIPSState *env, target_ulong val) if (env->insn_flags & ISA_MIPS32R6) { bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3; - +#if defined(TARGET_MIPS64) + uint32_t ksux = (1 << CP0St_KX) & val; + ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */ + ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */ + val = (val & ~(7 << CP0St_UX)) | ksux; +#endif if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) { mask &= ~(3 << CP0St_KSU); }