From patchwork Fri Sep 18 11:25:33 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leon Alrae X-Patchwork-Id: 519250 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4F3F1140216 for ; Fri, 18 Sep 2015 21:27:40 +1000 (AEST) Received: from localhost ([::1]:37144 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZctpJ-00076s-Vc for incoming@patchwork.ozlabs.org; Fri, 18 Sep 2015 07:27:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55497) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZctoN-0005Zb-Kd for qemu-devel@nongnu.org; Fri, 18 Sep 2015 07:26:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZctoM-0007ev-Im for qemu-devel@nongnu.org; Fri, 18 Sep 2015 07:26:39 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:23787) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZctoM-0007dR-DK for qemu-devel@nongnu.org; Fri, 18 Sep 2015 07:26:38 -0400 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id D9055B2BB8F38 for ; Fri, 18 Sep 2015 12:26:35 +0100 (IST) Received: from hhmail02.hh.imgtec.org (10.100.10.20) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.195.1; Fri, 18 Sep 2015 12:26:37 +0100 Received: from lalrae-linux.kl.imgtec.org (192.168.14.163) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.235.1; Fri, 18 Sep 2015 12:26:36 +0100 From: Leon Alrae To: Date: Fri, 18 Sep 2015 12:25:33 +0100 Message-ID: <1442575535-4735-9-git-send-email-leon.alrae@imgtec.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1442575535-4735-1-git-send-email-leon.alrae@imgtec.com> References: <1442575535-4735-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.14.163] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Subject: [Qemu-devel] [PULL 08/10] target-mips: add missing restriction in DAUI instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org rs cannot be the zero register, Reserved Instruction exception must be signalled for this case. Signed-off-by: Leon Alrae Reviewed-by: Aurelien Jarno --- target-mips/translate.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index cd0cf8b..0883782 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -19525,7 +19525,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) #if defined(TARGET_MIPS64) /* OPC_DAUI */ check_mips_64(ctx); - if (rt != 0) { + if (rs == 0) { + generate_exception(ctx, EXCP_RI); + } else if (rt != 0) { TCGv t0 = tcg_temp_new(); gen_load_gpr(t0, rs); tcg_gen_addi_tl(cpu_gpr[rt], t0, imm << 16);