From patchwork Fri Sep 18 11:25:34 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leon Alrae X-Patchwork-Id: 519253 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DF751401B5 for ; Fri, 18 Sep 2015 21:29:13 +1000 (AEST) Received: from localhost ([::1]:37159 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zctqp-0001Hb-BB for incoming@patchwork.ozlabs.org; Fri, 18 Sep 2015 07:29:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55511) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZctoO-0005aU-5X for qemu-devel@nongnu.org; Fri, 18 Sep 2015 07:26:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZctoN-0007hE-8A for qemu-devel@nongnu.org; Fri, 18 Sep 2015 07:26:40 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:61208) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZctoN-0007fz-2C for qemu-devel@nongnu.org; Fri, 18 Sep 2015 07:26:39 -0400 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id 210F1E49AD249 for ; Fri, 18 Sep 2015 12:26:36 +0100 (IST) Received: from hhmail02.hh.imgtec.org (10.100.10.20) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.195.1; Fri, 18 Sep 2015 12:26:38 +0100 Received: from lalrae-linux.kl.imgtec.org (192.168.14.163) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.235.1; Fri, 18 Sep 2015 12:26:37 +0100 From: Leon Alrae To: Date: Fri, 18 Sep 2015 12:25:34 +0100 Message-ID: <1442575535-4735-10-git-send-email-leon.alrae@imgtec.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1442575535-4735-1-git-send-email-leon.alrae@imgtec.com> References: <1442575535-4735-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.14.163] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Subject: [Qemu-devel] [PULL 09/10] target-mips: correct MTC0 instruction on MIPS64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org MTC0 on a 64-bit processor should move entire 64-bit GPR content to CP0 register. Signed-off-by: Leon Alrae Reviewed-by: Aurelien Jarno --- target-mips/translate.c | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index 0883782..a59b670 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -4765,12 +4765,6 @@ static inline void gen_mtc0_store32 (TCGv arg, target_ulong off) tcg_temp_free_i32(t0); } -static inline void gen_mtc0_store64 (TCGv arg, target_ulong off) -{ - tcg_gen_ext32s_tl(arg, arg); - tcg_gen_st_tl(arg, cpu_env, off); -} - static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel) { const char *rn = "invalid"; @@ -5629,12 +5623,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case 5: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_VPESchedule)); + tcg_gen_st_tl(arg, cpu_env, + offsetof(CPUMIPSState, CP0_VPESchedule)); rn = "VPESchedule"; break; case 6: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_VPEScheFBack)); + tcg_gen_st_tl(arg, cpu_env, + offsetof(CPUMIPSState, CP0_VPEScheFBack)); rn = "VPEScheFBack"; break; case 7: @@ -5884,7 +5880,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) case 14: switch (sel) { case 0: - gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_EPC)); + tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC)); rn = "EPC"; break; default: @@ -6057,7 +6053,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) switch (sel) { case 0: /* EJTAG support */ - gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_DEPC)); + tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC)); rn = "DEPC"; break; default: @@ -6160,7 +6156,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) case 30: switch (sel) { case 0: - gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_ErrorEPC)); + tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC)); rn = "ErrorEPC"; break; default: