From patchwork Mon Sep 14 12:58:24 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leon Alrae X-Patchwork-Id: 517391 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id EB79714012C for ; Mon, 14 Sep 2015 22:59:10 +1000 (AEST) Received: from localhost ([::1]:40560 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZbTLg-0002go-IX for incoming@patchwork.ozlabs.org; Mon, 14 Sep 2015 08:59:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36466) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZbTLD-000210-4J for qemu-devel@nongnu.org; Mon, 14 Sep 2015 08:58:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZbTL7-0005Z5-8u for qemu-devel@nongnu.org; Mon, 14 Sep 2015 08:58:39 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:47690) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZbTL7-0005Yq-2f for qemu-devel@nongnu.org; Mon, 14 Sep 2015 08:58:33 -0400 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id CC0BEE02C0EB0; Mon, 14 Sep 2015 13:58:29 +0100 (IST) Received: from hhmail02.hh.imgtec.org (10.100.10.20) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.195.1; Mon, 14 Sep 2015 13:58:32 +0100 Received: from lalrae-linux.kl.imgtec.org (192.168.14.163) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.235.1; Mon, 14 Sep 2015 13:58:31 +0100 From: Leon Alrae To: Date: Mon, 14 Sep 2015 13:58:24 +0100 Message-ID: <1442235504-15910-3-git-send-email-leon.alrae@imgtec.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1442235504-15910-1-git-send-email-leon.alrae@imgtec.com> References: <1442235504-15910-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.14.163] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Cc: aurelien@aurel32.net Subject: [Qemu-devel] [PATCH 2/2] target-mips: implement the CPU wake-up on non-enabled interrupts in R6 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org In Release 6, the behaviour of WAIT has been modified to make it a requirement that a processor that has disabled operation as a result of executing a WAIT will resume operation on arrival of an interrupt even if interrupts are not enabled. Signed-off-by: Leon Alrae --- target-mips/cpu.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/target-mips/cpu.c b/target-mips/cpu.c index 144eea9..cbeca04 100644 --- a/target-mips/cpu.c +++ b/target-mips/cpu.c @@ -53,12 +53,13 @@ static bool mips_cpu_has_work(CPUState *cs) CPUMIPSState *env = &cpu->env; bool has_work = false; - /* It is implementation dependent if non-enabled interrupts - wake-up the CPU, however most of the implementations only + /* Prior to MIPS Release 6 it is implementation dependent if non-enabled + interrupts wake-up the CPU, however most of the implementations only check for interrupts that can be taken. */ if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && cpu_mips_hw_interrupts_pending(env)) { - if (cpu_mips_hw_interrupts_enabled(env)) { + if (cpu_mips_hw_interrupts_enabled(env) || + (env->insn_flags & ISA_MIPS32R6)) { has_work = true; } }