From patchwork Sun Jun 21 11:56:14 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 487053 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 679F214012C for ; Sun, 21 Jun 2015 22:04:36 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=EqgpjJ0Y; dkim-atps=neutral Received: from localhost ([::1]:36080 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z6dzG-0007xP-K6 for incoming@patchwork.ozlabs.org; Sun, 21 Jun 2015 08:04:34 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39833) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z6dyY-000747-45 for qemu-devel@nongnu.org; Sun, 21 Jun 2015 08:03:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z6dyT-000242-35 for qemu-devel@nongnu.org; Sun, 21 Jun 2015 08:03:50 -0400 Received: from mail-pd0-x22c.google.com ([2607:f8b0:400e:c02::22c]:36312) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z6dyS-00023r-Fn for qemu-devel@nongnu.org; Sun, 21 Jun 2015 08:03:44 -0400 Received: by pdjm12 with SMTP id m12so120115583pdj.3 for ; Sun, 21 Jun 2015 05:03:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:subject:date:message-id:in-reply-to:references; bh=nCYI/AzMQkYLKrEWCbFLsgRb3DrNlLoKuzrqcx8kyZY=; b=EqgpjJ0YwzDJRwb3Zgge0dV9JWoDO0UTK5zKF+HwJtA8Z6kVlOC6wSeQjemhbDKeuh S8gVLhN5E5qq+7P2zBtg5VDx1Yea1HEu0QcUihsD9/jDR630dVLigH4DmLUdCTfmGi8+ Iatyr8IatbRXiVaYSUvc9APk1/kgUH2mgMrbrjjcR9PBePOqgbDcnNoyxyg86nsNdSeb h2ACCUaJJCnsgofkHuk+r3anMdOYTlxGC+hBPnC7vksTIWtlJCeHSfUdpnxFYl3TK1eI rFaFV6CCfRcw7tYVlNnOdcfx+7Gz16uU/SI1KrrH1ueEdLyK8UzmTKjeXFyVfUoqLRDJ vSBQ== X-Received: by 10.70.39.103 with SMTP id o7mr49119308pdk.122.1434888223736; Sun, 21 Jun 2015 05:03:43 -0700 (PDT) Received: from localhost ([203.126.243.116]) by mx.google.com with ESMTPSA id ld1sm16580200pbc.26.2015.06.21.05.03.42 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Sun, 21 Jun 2015 05:03:43 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Sun, 21 Jun 2015 21:56:14 +1000 Message-Id: <1434887787-4188-4-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1434887787-4188-1-git-send-email-edgar.iglesias@gmail.com> References: <1434887787-4188-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c02::22c Subject: [Qemu-devel] [PATCH v1 03/16] target-microblaze: Preserve the pvr registers during reset X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Alistair Francis Move the Microblaze PVR registers to the end of the CPUMBState and preserve them during reset. This is similar to what the QEMU ARM model does with some of it's registers. This allows the Microblaze PVR registers to only be set once at realise instead of constantly at reset. Signed-off-by: Alistair Francis Reviewed-by: Peter Crosthwaite Reviewed-by: Edgar E. Iglesias Signed-off-by: Edgar E. Iglesias --- target-microblaze/cpu.c | 40 ++++++++++++++++++++++------------------ target-microblaze/cpu.h | 10 ++++++---- 2 files changed, 28 insertions(+), 22 deletions(-) diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c index 67e3182..95be540 100644 --- a/target-microblaze/cpu.c +++ b/target-microblaze/cpu.c @@ -63,13 +63,34 @@ static void mb_cpu_reset(CPUState *s) mcc->parent_reset(s); - memset(env, 0, sizeof(CPUMBState)); + memset(env, 0, offsetof(CPUMBState, pvr)); env->res_addr = RES_ADDR_NONE; tlb_flush(s, 1); /* Disable stack protector. */ env->shr = ~0; +#if defined(CONFIG_USER_ONLY) + /* start in user mode with interrupts enabled. */ + env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM; +#else + env->sregs[SR_MSR] = 0; + mmu_init(&env->mmu); + env->mmu.c_mmu = 3; + env->mmu.c_mmu_tlb_access = 3; + env->mmu.c_mmu_zones = 16; +#endif +} + +static void mb_cpu_realizefn(DeviceState *dev, Error **errp) +{ + CPUState *cs = CPU(dev); + MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev); + MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); + CPUMBState *env = &cpu->env; + + qemu_init_vcpu(cs); + env->pvr.regs[0] = PVR0_PVR_FULL_MASK \ | PVR0_USE_BARREL_MASK \ | PVR0_USE_DIV_MASK \ @@ -99,25 +120,8 @@ static void mb_cpu_reset(CPUState *s) env->sregs[SR_PC] = cpu->base_vectors; #if defined(CONFIG_USER_ONLY) - /* start in user mode with interrupts enabled. */ - env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM; env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp. */ -#else - env->sregs[SR_MSR] = 0; - mmu_init(&env->mmu); - env->mmu.c_mmu = 3; - env->mmu.c_mmu_tlb_access = 3; - env->mmu.c_mmu_zones = 16; #endif -} - -static void mb_cpu_realizefn(DeviceState *dev, Error **errp) -{ - CPUState *cs = CPU(dev); - MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev); - - cpu_reset(cs); - qemu_init_vcpu(cs); mcc->parent_realize(dev, errp); } diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h index d73e1c7..534e1cf 100644 --- a/target-microblaze/cpu.h +++ b/target-microblaze/cpu.h @@ -260,16 +260,18 @@ struct CPUMBState { #define IFLAGS_TB_MASK (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG) uint32_t iflags; - struct { - uint32_t regs[16]; - } pvr; - #if !defined(CONFIG_USER_ONLY) /* Unified MMU. */ struct microblaze_mmu mmu; #endif CPU_COMMON + + /* These fields are preserved on reset. */ + + struct { + uint32_t regs[16]; + } pvr; }; #include "cpu-qom.h"