From patchwork Wed Jun 10 20:03:25 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Herv=C3=A9_Poussineau?= X-Patchwork-Id: 482856 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 5EC3D140285 for ; Thu, 11 Jun 2015 06:08:35 +1000 (AEST) Received: from localhost ([::1]:42145 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z2mIb-0002NM-Fq for incoming@patchwork.ozlabs.org; Wed, 10 Jun 2015 16:08:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36092) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z2mIF-0001mZ-0z for qemu-devel@nongnu.org; Wed, 10 Jun 2015 16:08:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z2mI9-0000w6-SE for qemu-devel@nongnu.org; Wed, 10 Jun 2015 16:08:10 -0400 Received: from smtp2-g21.free.fr ([212.27.42.2]:3951) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z2mI9-0000vP-Mp for qemu-devel@nongnu.org; Wed, 10 Jun 2015 16:08:05 -0400 Received: from localhost.localdomain (unknown [82.227.227.196]) by smtp2-g21.free.fr (Postfix) with ESMTP id C58EB4B01F7; Wed, 10 Jun 2015 22:05:44 +0200 (CEST) From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= To: qemu-devel@nongnu.org Date: Wed, 10 Jun 2015 22:03:25 +0200 Message-Id: <1433966605-14968-1-git-send-email-hpoussin@reactos.org> X-Mailer: git-send-email 2.1.4 MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Windows NT kernel [generic] [fuzzy] X-Received-From: 212.27.42.2 Cc: Leon Alrae , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Aurelien Jarno Subject: [Qemu-devel] [PATCH] gt64xxx: access right I/O port when activating byte swapping X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Incidentally, this fixes YAMON on big endian guest. Signed-off-by: Hervé Poussineau --- hw/mips/gt64xxx_pci.c | 62 +++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 60 insertions(+), 2 deletions(-) diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 10fcca3..39dd8ff 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -176,6 +176,7 @@ /* PCI Internal */ #define GT_PCI0_CMD (0xc00 >> 2) +#define GT_CMD_MWORDSWAP (1 << 10) #define GT_PCI0_TOR (0xc04 >> 2) #define GT_PCI0_BS_SCS10 (0xc08 >> 2) #define GT_PCI0_BS_SCS32 (0xc0c >> 2) @@ -292,6 +293,62 @@ static void gt64120_isd_mapping(GT64120State *s) memory_region_add_subregion(get_system_memory(), s->ISD_start, &s->ISD_mem); } +static uint64_t gt64120_pci_io_read(void *opaque, hwaddr addr, + unsigned int size) +{ + GT64120State *s = opaque; + uint8_t buf[4]; + + if (s->regs[GT_PCI0_CMD] & GT_CMD_MWORDSWAP) { + addr = (addr & ~3) + 4 - size - (addr & 3); + } + + address_space_read(&address_space_io, addr, MEMTXATTRS_UNSPECIFIED, + buf, size); + + if (size == 1) { + return buf[0]; + } else if (size == 2) { + return lduw_le_p(buf); + } else if (size == 4) { + return ldl_le_p(buf); + } else { + g_assert_not_reached(); + } +} + +static void gt64120_pci_io_write(void *opaque, hwaddr addr, uint64_t data, + unsigned int size) +{ + GT64120State *s = opaque; + uint8_t buf[4]; + + if (s->regs[GT_PCI0_CMD] & GT_CMD_MWORDSWAP) { + addr = (addr & ~3) + 4 - size - (addr & 3); + } + + if (size == 1) { + buf[0] = data; + } else if (size == 2) { + stw_le_p(buf, data); + } else if (size == 4) { + stl_le_p(buf, data); + } else { + g_assert_not_reached(); + } + + address_space_write(&address_space_io, addr, MEMTXATTRS_UNSPECIFIED, + buf, size); +} + +static const MemoryRegionOps gt64120_pci_io_ops = { + .read = gt64120_pci_io_read, + .write = gt64120_pci_io_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .impl.max_access_size = 4, + .valid.unaligned = true, +}; + static void gt64120_pci_mapping(GT64120State *s) { /* Update PCI0IO mapping */ @@ -306,8 +363,9 @@ static void gt64120_pci_mapping(GT64120State *s) s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI0IOLD] & 0x7f)) << 21; if (s->PCI0IO_length) { - memory_region_init_alias(&s->PCI0IO_mem, OBJECT(s), "pci0-io", - get_system_io(), 0, s->PCI0IO_length); + memory_region_init_io(&s->PCI0IO_mem, OBJECT(s), + >64120_pci_io_ops, + s, "pci0-io", s->PCI0IO_length); memory_region_add_subregion(get_system_memory(), s->PCI0IO_start, &s->PCI0IO_mem); }