From patchwork Fri Jun 5 10:33:39 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 481143 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id D4485140218 for ; Fri, 5 Jun 2015 20:42:51 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=plkIIXHo; dkim-atps=neutral Received: from localhost ([::1]:46351 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0p5N-00036o-PR for incoming@patchwork.ozlabs.org; Fri, 05 Jun 2015 06:42:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50219) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0p3c-00008b-6L for qemu-devel@nongnu.org; Fri, 05 Jun 2015 06:41:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z0p3W-0001yt-0p for qemu-devel@nongnu.org; Fri, 05 Jun 2015 06:41:00 -0400 Received: from mail-qk0-x22f.google.com ([2607:f8b0:400d:c09::22f]:36591) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0p3V-0001yl-QR for qemu-devel@nongnu.org; Fri, 05 Jun 2015 06:40:53 -0400 Received: by qkx62 with SMTP id 62so38191524qkx.3 for ; Fri, 05 Jun 2015 03:40:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2tPYRZxKj50jOqaeLeVYDojTkKQy11aREjh5JrFr6Ac=; b=plkIIXHozhVCki3Y6MCVHshpVHbOFmxjL4pyptxBNldcZBjEnHPRfHcsnnp1pUXpJ/ cREXtuzsDd8x039JnrsCtCKSb640V/nbwcx50lt5bA/TdAfhTgP4ANJSGmmQf69e4iei +76sJZHS7ZIH09FpJ2DcBkHvZvzIpTc2UhM7nOmFWoxlX1kqL3OEZbG3p/HEB5Wa6bcm /eajUt7z1eZtFx8XBKgPsLtUI2MqpR3ETgieV/rCtV5K6rE1pX9QXjGfo4lYUXhE8MLY k6w/6r/e33zjsU9CwGV/gtbOJyElB8836fwQf7/sdMe2fAsBeK55kZM1HbH26bTWU1NY dWCQ== X-Received: by 10.140.165.150 with SMTP id l144mr3158903qhl.99.1433500853428; Fri, 05 Jun 2015 03:40:53 -0700 (PDT) Received: from localhost ([203.126.243.116]) by mx.google.com with ESMTPSA id g201sm3769161qhc.6.2015.06.05.03.40.52 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 05 Jun 2015 03:40:53 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Fri, 5 Jun 2015 20:33:39 +1000 Message-Id: <1433500421-22879-5-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1433500421-22879-1-git-send-email-edgar.iglesias@gmail.com> References: <1433500421-22879-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400d:c09::22f Cc: edgar.iglesias@xilinx.com, serge.fdrv@gmail.com, alex.bennee@linaro.org, agraf@suse.de Subject: [Qemu-devel] [PATCH v4 4/6] target-arm: Add the Hypervisor timer X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: "Edgar E. Iglesias" Signed-off-by: Edgar E. Iglesias --- target-arm/cpu-qom.h | 1 + target-arm/cpu.c | 2 ++ target-arm/cpu.h | 3 ++- target-arm/helper.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 69 insertions(+), 1 deletion(-) diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index ed5a644..3aaa7b6 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -214,6 +214,7 @@ int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); /* Callback functions for the generic timer's timers. */ void arm_gt_ptimer_cb(void *opaque); void arm_gt_vtimer_cb(void *opaque); +void arm_gt_htimer_cb(void *opaque); #ifdef TARGET_AARCH64 int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 4a888ab..b631482 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -409,6 +409,8 @@ static void arm_cpu_initfn(Object *obj) arm_gt_ptimer_cb, cpu); cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, arm_gt_vtimer_cb, cpu); + cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, + arm_gt_htimer_cb, cpu); qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, ARRAY_SIZE(cpu->gt_timer_outputs)); #endif diff --git a/target-arm/cpu.h b/target-arm/cpu.h index f39c32b..dfa9d77 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -113,7 +113,8 @@ typedef struct ARMGenericTimer { #define GTIMER_PHYS 0 #define GTIMER_VIRT 1 -#define NUM_GTIMERS 2 +#define GTIMER_HYP 2 +#define NUM_GTIMERS 3 typedef struct { uint64_t raw_tcr; diff --git a/target-arm/helper.c b/target-arm/helper.c index 410e814..aafb5d4 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1400,6 +1400,34 @@ static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri, gt_recalc_timer(cpu, GTIMER_VIRT); } +static void gt_hyp_cnt_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + gt_cnt_reset(env, ri, GTIMER_HYP); +} + +static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_cval_write(env, ri, GTIMER_HYP, value); +} + +static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return gt_tval_read(env, ri, GTIMER_HYP); +} + +static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_tval_write(env, ri, GTIMER_HYP, value); +} + +static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_ctl_write(env, ri, GTIMER_HYP, value); +} + void arm_gt_ptimer_cb(void *opaque) { ARMCPU *cpu = opaque; @@ -1414,6 +1442,13 @@ void arm_gt_vtimer_cb(void *opaque) gt_recalc_timer(cpu, GTIMER_VIRT); } +void arm_gt_htimer_cb(void *opaque) +{ + ARMCPU *cpu = opaque; + + gt_recalc_timer(cpu, GTIMER_HYP); +} + static const ARMCPRegInfo generic_timer_cp_reginfo[] = { /* Note that CNTFRQ is purely reads-as-written for the benefit * of software; writing it doesn't actually change the timer frequency. @@ -2648,6 +2683,18 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14, .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, .resetvalue = 0 }, + { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, + .access = PL2_RW, + .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore, }, + { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2, + .access = PL2_RW, + .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore, }, + { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0, + .access = PL2_RW, + .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore, }, REGINFO_SENTINEL }; @@ -2774,6 +2821,23 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_IO, .writefn = gt_cntvoff_write, .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) }, + { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_AA64, + .type = ARM_CP_IO, + .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, + .access = PL2_RW, + .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ctl), + .resetvalue = 0, + .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write }, + { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2, + .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), + .type = ARM_CP_IO, .access = PL2_RW, + .writefn = gt_hyp_cval_write, .raw_writefn = raw_write }, + { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0, + .type = ARM_CP_IO, .access = PL2_RW, + .resetfn = gt_hyp_cnt_reset, + .readfn = gt_hyp_tval_read, .writefn = gt_hyp_tval_write }, #endif REGINFO_SENTINEL };