From patchwork Wed Jun 3 09:32:34 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leon Alrae X-Patchwork-Id: 479840 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id C3BD9140280 for ; Wed, 3 Jun 2015 19:33:38 +1000 (AEST) Received: from localhost ([::1]:34229 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z053I-00083C-Up for incoming@patchwork.ozlabs.org; Wed, 03 Jun 2015 05:33:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54758) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z052g-0006lf-HB for qemu-devel@nongnu.org; Wed, 03 Jun 2015 05:32:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z052c-0007qK-Po for qemu-devel@nongnu.org; Wed, 03 Jun 2015 05:32:58 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:47647) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z052c-0007pr-K5 for qemu-devel@nongnu.org; Wed, 03 Jun 2015 05:32:54 -0400 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id 6FA68EED6806D; Wed, 3 Jun 2015 10:32:51 +0100 (IST) Received: from lalrae-linux.kl.imgtec.org (192.168.14.163) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.195.1; Wed, 3 Jun 2015 10:32:53 +0100 From: Leon Alrae To: Date: Wed, 3 Jun 2015 10:32:34 +0100 Message-ID: <1433323956-7867-6-git-send-email-leon.alrae@imgtec.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1433323956-7867-1-git-send-email-leon.alrae@imgtec.com> References: <1433323956-7867-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.14.163] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Cc: james.hogan@imgtec.com, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH v2 5/7] target-mips: correct MFC0 for CP0.EntryLo in MIPS64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Since PFNX is now supported the bits 31:30 have to be cleared. Signed-off-by: Leon Alrae --- target-mips/translate.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index c931eda..0ca610c 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -5169,10 +5169,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo0)); #if defined(TARGET_MIPS64) if (ctx->rxi) { + /* Move RI/XI fields to bits 31:30 */ TCGv tmp = tcg_temp_new(); - tcg_gen_andi_tl(tmp, arg, (3ull << CP0EnLo_XI)); - tcg_gen_shri_tl(tmp, tmp, 32); - tcg_gen_or_tl(arg, arg, tmp); + tcg_gen_shri_tl(tmp, arg, CP0EnLo_XI); + tcg_gen_deposit_tl(arg, arg, tmp, 30, 2); tcg_temp_free(tmp); } #endif @@ -5224,10 +5224,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo1)); #if defined(TARGET_MIPS64) if (ctx->rxi) { + /* Move RI/XI fields to bits 31:30 */ TCGv tmp = tcg_temp_new(); - tcg_gen_andi_tl(tmp, arg, (3ull << CP0EnLo_XI)); - tcg_gen_shri_tl(tmp, tmp, 32); - tcg_gen_or_tl(arg, arg, tmp); + tcg_gen_shri_tl(tmp, arg, CP0EnLo_XI); + tcg_gen_deposit_tl(arg, arg, tmp, 30, 2); tcg_temp_free(tmp); } #endif