From patchwork Fri May 29 06:43:17 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 477601 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id D902E14012C for ; Fri, 29 May 2015 16:51:40 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=ih75jqxX; dkim-atps=neutral Received: from localhost ([::1]:33900 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YyE8o-0004A0-PZ for incoming@patchwork.ozlabs.org; Fri, 29 May 2015 02:51:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58524) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YyE8B-00034I-E4 for qemu-devel@nongnu.org; Fri, 29 May 2015 02:51:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YyE87-00026R-Ho for qemu-devel@nongnu.org; Fri, 29 May 2015 02:50:59 -0400 Received: from mail-pa0-x22b.google.com ([2607:f8b0:400e:c03::22b]:34933) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YyE87-000262-6r for qemu-devel@nongnu.org; Fri, 29 May 2015 02:50:55 -0400 Received: by pacwv17 with SMTP id wv17so46030019pac.2 for ; Thu, 28 May 2015 23:50:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5QPXohvvgKUHwuWvL5389/8DBzDxvNulRO+I+eXPDsQ=; b=ih75jqxXQzQM3GikM1JlIC3oAyX4H6FR1dwc9qKqzfZur/mAotYvgLXnaDc+QRCq1u dH9Ol60njYDAtOG9uup09E4Q9PvV4kMqTPtddooFyNzPpm724HuNAsRYpImER078Ba4q IhyYXpGL/SbRvUZZR/cyS4ax8rUWKatgLdUGGyb+PR02/odOsxZJotQGwLunUonMPvNw I/HKDMZOs3LSyWse/dB5KTG4YgIs/NzlWDL/CweEJOxrQAahxXB7Ab1YSHgNZnzA3dIo nR6hLEIYvg5ag0I4LmWrE4+owI0YI6B5j+7CMgfOaPgl9/7OtoiwPF7OVdmyvDsshee3 /fgw== X-Received: by 10.70.101.200 with SMTP id fi8mr12314595pdb.161.1432882254208; Thu, 28 May 2015 23:50:54 -0700 (PDT) Received: from localhost ([203.126.243.116]) by mx.google.com with ESMTPSA id ae9sm4443093pac.25.2015.05.28.23.50.52 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 28 May 2015 23:50:53 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Fri, 29 May 2015 16:43:17 +1000 Message-Id: <1432881807-18164-6-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1432881807-18164-1-git-send-email-edgar.iglesias@gmail.com> References: <1432881807-18164-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c03::22b Cc: edgar.iglesias@xilinx.com, serge.fdrv@gmail.com, alex.bennee@linaro.org, agraf@suse.de Subject: [Qemu-devel] [PATCH v3 05/15] target-arm: Add SCTLR_EL2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: "Edgar E. Iglesias" Signed-off-by: Edgar E. Iglesias --- target-arm/helper.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index 7dadc8a..334e008 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2527,6 +2527,9 @@ static const ARMCPRegInfo v8_el3_no_el2_cp_reginfo[] = { { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, + .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, + .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, REGINFO_SENTINEL }; @@ -2611,6 +2614,10 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { .access = PL2_RW, .writefn = vmsa_tcr_el1_write, .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write, .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, + { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, + .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, + .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write, + .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) }, REGINFO_SENTINEL };