From patchwork Wed May 27 07:27:29 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 476964 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4827814029C for ; Wed, 27 May 2015 17:35:02 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=yPiZsgrE; dkim-atps=neutral Received: from localhost ([::1]:52264 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YxVrg-0003QL-Fc for incoming@patchwork.ozlabs.org; Wed, 27 May 2015 03:35:00 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46278) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YxVrF-0002gT-Bc for qemu-devel@nongnu.org; Wed, 27 May 2015 03:34:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YxVrC-0005ty-4O for qemu-devel@nongnu.org; Wed, 27 May 2015 03:34:33 -0400 Received: from mail-oi0-x22c.google.com ([2607:f8b0:4003:c06::22c]:35307) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YxVrB-0005tg-Tr for qemu-devel@nongnu.org; Wed, 27 May 2015 03:34:30 -0400 Received: by oihd6 with SMTP id d6so1175826oih.2 for ; Wed, 27 May 2015 00:34:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5QPXohvvgKUHwuWvL5389/8DBzDxvNulRO+I+eXPDsQ=; b=yPiZsgrE8gZxLfYfaTd7mNR+8OJSMb7qZQxdSvajShRP4ddv65uu46orBek9H9Xodz s2UYgBjamb0oUXrDd4sq7dZbRLKrp2vYAAn70o2rGbVbo7dYQnV56IR7V2Ly97di4A9O z/qibCJGDGur8JhHPzopWEwPN0jn5PXogj8tqnKGr8tidVEM70gEDmX57BYuVsR0B5Sb yDsfJfTGYX7fnhgoUgBMKQg2pn/Did5M36dOWWIt2J6axtQKq0bBx7nMR/qh6IOcBQjD C9jsomfYTIxRQEIAIUXVwwandLZqZywH6TiEn5fqD3KNJM5Dhn2oBW0lfsL9DJrcs+ex zMqQ== X-Received: by 10.60.56.73 with SMTP id y9mr2767879oep.25.1432712069207; Wed, 27 May 2015 00:34:29 -0700 (PDT) Received: from localhost ([203.126.243.116]) by mx.google.com with ESMTPSA id mu5sm10480014obc.4.2015.05.27.00.34.28 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Wed, 27 May 2015 00:34:28 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Wed, 27 May 2015 17:27:29 +1000 Message-Id: <1432711659-24591-5-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1432711659-24591-1-git-send-email-edgar.iglesias@gmail.com> References: <1432711659-24591-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:4003:c06::22c Cc: edgar.iglesias@xilinx.com, serge.fdrv@gmail.com, alex.bennee@linaro.org, agraf@suse.de, greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v2 04/14] target-arm: Add SCTLR_EL2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: "Edgar E. Iglesias" Signed-off-by: Edgar E. Iglesias --- target-arm/helper.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index 7dadc8a..334e008 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2527,6 +2527,9 @@ static const ARMCPRegInfo v8_el3_no_el2_cp_reginfo[] = { { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, + .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, + .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, REGINFO_SENTINEL }; @@ -2611,6 +2614,10 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { .access = PL2_RW, .writefn = vmsa_tcr_el1_write, .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write, .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, + { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, + .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, + .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write, + .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) }, REGINFO_SENTINEL };