From patchwork Wed May 27 07:27:28 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 476963 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id BEB8D14016A for ; Wed, 27 May 2015 17:34:23 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=1AMHxVTG; dkim-atps=neutral Received: from localhost ([::1]:52259 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YxVr3-0002Nc-UC for incoming@patchwork.ozlabs.org; Wed, 27 May 2015 03:34:21 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46143) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YxVqh-0001oL-6l for qemu-devel@nongnu.org; Wed, 27 May 2015 03:34:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YxVqc-0005hi-66 for qemu-devel@nongnu.org; Wed, 27 May 2015 03:33:59 -0400 Received: from mail-ob0-x230.google.com ([2607:f8b0:4003:c01::230]:35754) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YxVqb-0005ha-TR for qemu-devel@nongnu.org; Wed, 27 May 2015 03:33:54 -0400 Received: by obbgf1 with SMTP id gf1so1164110obb.2 for ; Wed, 27 May 2015 00:33:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=geE8UfoDORJBD7uvVoNG+TPzM9mItlrO+gEzoJRFidk=; b=1AMHxVTGDrcAvG+S4R076jyXdoVoh1aiQkiIqU0QWNkCEjiGTxg9d4RbSTY7460uNI 6aAUGBGxr8/TzcBG9JBBTKwpfXcEE61/7tatVjQtKYGqjdd+bZwslJ2Yi+PafOX1EYL5 0RvSv6li4YPdawNGtMijTO4YmgNyjIcWbvSviXPRJQ+mvsqHiy9+GDdM6vzxDSV3Xgcq nswqdS38BREE1W4M0iJfhK63smrOjN2+nC2/mvGRMHPF2mlytyUuYAm1XPktRXpOOv3p /53urJjaEsLCccdGnewqYRPP8+jehsr1XvjBT5AuPYRqwbybjT85SJYahmlpY6yvySb0 5NyQ== X-Received: by 10.182.73.168 with SMTP id m8mr25211054obv.58.1432712033158; Wed, 27 May 2015 00:33:53 -0700 (PDT) Received: from localhost ([203.126.243.116]) by mx.google.com with ESMTPSA id x123sm9967154oie.25.2015.05.27.00.33.51 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Wed, 27 May 2015 00:33:52 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Wed, 27 May 2015 17:27:28 +1000 Message-Id: <1432711659-24591-4-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1432711659-24591-1-git-send-email-edgar.iglesias@gmail.com> References: <1432711659-24591-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:4003:c01::230 Cc: edgar.iglesias@xilinx.com, serge.fdrv@gmail.com, alex.bennee@linaro.org, agraf@suse.de, greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v2 03/14] target-arm: Add TCR_EL2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: "Edgar E. Iglesias" Signed-off-by: Edgar E. Iglesias --- target-arm/helper.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index 427cfab..7dadc8a 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2524,6 +2524,9 @@ static const ARMCPRegInfo v8_el3_no_el2_cp_reginfo[] = { { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, + .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, + .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, REGINFO_SENTINEL }; @@ -2603,6 +2606,11 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, .access = PL2_RW, .type = ARM_CP_ALIAS, .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) }, + { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, + .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, + .access = PL2_RW, .writefn = vmsa_tcr_el1_write, + .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write, + .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, REGINFO_SENTINEL };