From patchwork Fri Apr 24 10:26:52 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Hogan X-Patchwork-Id: 464161 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 496F9140134 for ; Fri, 24 Apr 2015 20:27:47 +1000 (AEST) Received: from localhost ([::1]:44005 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ylapl-0006Z1-GV for incoming@patchwork.ozlabs.org; Fri, 24 Apr 2015 06:27:45 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54297) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YlapQ-00060Z-9Q for qemu-devel@nongnu.org; Fri, 24 Apr 2015 06:27:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YlapM-000803-Ma for qemu-devel@nongnu.org; Fri, 24 Apr 2015 06:27:24 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:9687) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YlapM-0007zf-HP; Fri, 24 Apr 2015 06:27:20 -0400 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id ABCBE9EF3451C; Fri, 24 Apr 2015 11:27:15 +0100 (IST) Received: from LEMAIL01.le.imgtec.org (192.168.152.62) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.195.1; Fri, 24 Apr 2015 11:27:17 +0100 Received: from jhogan-linux.le.imgtec.org (192.168.154.110) by LEMAIL01.le.imgtec.org (192.168.152.62) with Microsoft SMTP Server (TLS) id 14.3.210.2; Fri, 24 Apr 2015 11:27:17 +0100 From: James Hogan To: , Paolo Bonzini Date: Fri, 24 Apr 2015 11:26:52 +0100 Message-ID: <1429871214-23514-2-git-send-email-james.hogan@imgtec.com> X-Mailer: git-send-email 2.0.5 In-Reply-To: <1429871214-23514-1-git-send-email-james.hogan@imgtec.com> References: <1429871214-23514-1-git-send-email-james.hogan@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.154.110] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Cc: James Hogan , Leon Alrae , kvm@vger.kernel.org, Aurelien Jarno , qemu-stable@nongnu.org Subject: [Qemu-devel] [PATCH 1/2] mips/kvm: Fix Big endian 32-bit register access X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Fix access to 32-bit registers on big endian targets. The pointer passed to the kernel must be for the actual 32-bit value, not a temporary 64-bit value, otherwise on big endian systems the kernel will only interpret the upper half. Signed-off-by: James Hogan Cc: Paolo Bonzini Cc: Leon Alrae Cc: Aurelien Jarno Cc: kvm@vger.kernel.org Cc: qemu-stable@nongnu.org --- target-mips/kvm.c | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/target-mips/kvm.c b/target-mips/kvm.c index 4d1f7ead8142..1597bbeac17a 100644 --- a/target-mips/kvm.c +++ b/target-mips/kvm.c @@ -240,10 +240,9 @@ int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level) static inline int kvm_mips_put_one_reg(CPUState *cs, uint64_t reg_id, int32_t *addr) { - uint64_t val64 = *addr; struct kvm_one_reg cp0reg = { .id = reg_id, - .addr = (uintptr_t)&val64 + .addr = (uintptr_t)addr }; return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg); @@ -275,18 +274,12 @@ static inline int kvm_mips_put_one_reg64(CPUState *cs, uint64_t reg_id, static inline int kvm_mips_get_one_reg(CPUState *cs, uint64_t reg_id, int32_t *addr) { - int ret; - uint64_t val64 = 0; struct kvm_one_reg cp0reg = { .id = reg_id, - .addr = (uintptr_t)&val64 + .addr = (uintptr_t)addr }; - ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg); - if (ret >= 0) { - *addr = val64; - } - return ret; + return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg); } static inline int kvm_mips_get_one_ulreg(CPUState *cs, uint64 reg_id,