From patchwork Wed Feb 18 14:51:55 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leon Alrae X-Patchwork-Id: 440991 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 7014B140082 for ; Thu, 19 Feb 2015 02:10:05 +1100 (AEDT) Received: from localhost ([::1]:51388 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YO6GJ-0001Yl-Gv for incoming@patchwork.ozlabs.org; Wed, 18 Feb 2015 10:10:03 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54831) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YO6Fz-00012n-M5 for qemu-devel@nongnu.org; Wed, 18 Feb 2015 10:09:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YO6Fu-00043U-LQ for qemu-devel@nongnu.org; Wed, 18 Feb 2015 10:09:43 -0500 Received: from mailapp01.imgtec.com ([195.59.15.196]:64244) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YO5zB-0006yD-9s for qemu-devel@nongnu.org; Wed, 18 Feb 2015 09:52:21 -0500 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id 1AFF062D97B5B; Wed, 18 Feb 2015 14:52:17 +0000 (GMT) Received: from lalrae-linux.kl.imgtec.org (192.168.14.163) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.195.1; Wed, 18 Feb 2015 14:52:19 +0000 From: Leon Alrae To: Date: Wed, 18 Feb 2015 14:51:55 +0000 Message-ID: <1424271115-7885-3-git-send-email-leon.alrae@imgtec.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1424271115-7885-1-git-send-email-leon.alrae@imgtec.com> References: <1424271115-7885-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.14.163] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Cc: amit.shah@redhat.com, aurelien@aurel32.net, macro@linux-mips.org, quintela@redhat.com Subject: [Qemu-devel] [PATCH 2/2] target-mips: add missing MSA and correct FP in VMState X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Correct the structure and store MSA and FP flush_to_zero. Signed-off-by: Leon Alrae --- target-mips/machine.c | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/target-mips/machine.c b/target-mips/machine.c index 8d75962..c08e593 100644 --- a/target-mips/machine.c +++ b/target-mips/machine.c @@ -6,15 +6,23 @@ static int get_fpr(QEMUFile *f, void *pv, size_t size) { + int i; fpr_t *v = pv; - qemu_get_be64s(f, &v->d); + /* Restore entire MSA vector register */ + for (i = 0; i < MSA_WRLEN/64; i++) { + qemu_get_sbe64s(f, &v->wr.d[i]); + } return 0; } static void put_fpr(QEMUFile *f, void *pv, size_t size) { + int i; fpr_t *v = pv; - qemu_put_be64s(f, &v->d); + /* Save entire MSA vector register */ + for (i = 0; i < MSA_WRLEN/64; i++) { + qemu_put_sbe64s(f, &v->wr.d[i]); + } } const VMStateInfo vmstate_info_fpr = { @@ -31,7 +39,7 @@ const VMStateInfo vmstate_info_fpr = { static VMStateField vmstate_fpu_fields[] = { VMSTATE_FPR_ARRAY(fpr, CPUMIPSFPUContext, 32), - VMSTATE_INT8(fp_status.float_detect_tininess, CPUMIPSFPUContext), + VMSTATE_UINT8(fp_status.flush_to_zero, CPUMIPSFPUContext), VMSTATE_INT8(fp_status.float_rounding_mode, CPUMIPSFPUContext), VMSTATE_INT8(fp_status.float_exception_flags, CPUMIPSFPUContext), VMSTATE_UINT32(fcr0, CPUMIPSFPUContext), @@ -70,6 +78,11 @@ static VMStateField vmstate_tc_fields[] = { VMSTATE_UINTTL(CP0_TCScheFBack, TCState), VMSTATE_INT32(CP0_Debug_tcstatus, TCState), VMSTATE_UINTTL(CP0_UserLocal, TCState), + VMSTATE_INT32(msacsr, TCState), + VMSTATE_INT8(msa_fp_status.float_rounding_mode, TCState), + VMSTATE_INT8(msa_fp_status.float_exception_flags, TCState), + VMSTATE_UINT8(msa_fp_status.flush_to_zero, TCState), + VMSTATE_UINT8(msa_fp_status.flush_inputs_to_zero, TCState), VMSTATE_END_OF_LIST() }; @@ -183,8 +196,8 @@ const VMStateDescription vmstate_tlb = { const VMStateDescription vmstate_mips_cpu = { .name = "cpu", - .version_id = 5, - .minimum_version_id = 5, + .version_id = 6, + .minimum_version_id = 6, .fields = (VMStateField[]) { /* active TC */ VMSTATE_STRUCT(env.active_tc, MIPSCPU, 1, vmstate_tc, TCState),