From patchwork Tue Dec 16 19:48:49 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leon Alrae X-Patchwork-Id: 422032 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 276C31400DE for ; Wed, 17 Dec 2014 06:53:07 +1100 (AEDT) Received: from localhost ([::1]:46492 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y0yB7-00014D-Ca for incoming@patchwork.ozlabs.org; Tue, 16 Dec 2014 14:53:05 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47563) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y0y8G-0004ZU-VW for qemu-devel@nongnu.org; Tue, 16 Dec 2014 14:50:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Y0y8C-0002ZJ-Bc for qemu-devel@nongnu.org; Tue, 16 Dec 2014 14:50:08 -0500 Received: from mailapp01.imgtec.com ([195.59.15.196]:53971) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y0y8C-0002Xb-4C for qemu-devel@nongnu.org; Tue, 16 Dec 2014 14:50:04 -0500 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id 71B8A1D721375; Tue, 16 Dec 2014 19:49:59 +0000 (GMT) Received: from lalrae-linux.kl.imgtec.org (192.168.14.163) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.195.1; Tue, 16 Dec 2014 19:50:02 +0000 From: Leon Alrae To: Date: Tue, 16 Dec 2014 19:48:49 +0000 Message-ID: <1418759356-14242-4-git-send-email-leon.alrae@imgtec.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1418759356-14242-1-git-send-email-leon.alrae@imgtec.com> References: <1418759356-14242-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.14.163] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Cc: "Maciej W. Rozycki" Subject: [Qemu-devel] [PULL 03/30] target-mips: Add 5KEc and 5KEf MIPS64r2 processors X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: "Maciej W. Rozycki" Add the 5KEc and 5KEf processors from MIPS Technologies that are the original implementation of the MIPS64r2 ISA. Silicon for these processors has never been taped out and no soft cores were released even. They do exist though, a CP0.PRId value has been assigned and experimental RTLs produced at the time the MIPS64r2 ISA has been finalized. The settings introduced here faithfully reproduce that hardware. As far the implementation goes these processors are the same as the 5Kc and the 5Kf CPUs respectively, except implementing the MIPS64r2 rather than the original MIPS64 instruction set. There must have been some updates to the CP0 architecture as mandated by the ISA, such as the addition of the EBase register, although I am not sure about the exact details, no documentation has ever been produced for these processors. The remaining parts of the microarchitecture, in particular the pipeline, stayed unchanged. Or to put it another way, the difference between a 5K and a 5KE CPU corresponds to one between a 4K and a 4KE CPU, except for the 64-bit rather than 32-bit ISA. Signed-off-by: Maciej W. Rozycki Signed-off-by: Leon Alrae --- target-mips/translate_init.c | 45 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 148b394..607f1c8 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -520,6 +520,51 @@ static const mips_def_t mips_defs[] = .mmu_type = MMU_TYPE_R4000, }, { + .name = "5KEc", + .CP0_PRid = 0x00018900, + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) | + (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | + (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | + (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3, + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x32F8FFFF, + .SEGBITS = 42, + .PABITS = 36, + .insn_flags = CPU_MIPS64R2, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "5KEf", + .CP0_PRid = 0x00018900, + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) | + (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | + (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | + (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3, + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x36F8FFFF, + .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | + (1 << FCR0_D) | (1 << FCR0_S) | + (0x89 << FCR0_PRID) | (0x0 << FCR0_REV), + .SEGBITS = 42, + .PABITS = 36, + .insn_flags = CPU_MIPS64R2, + .mmu_type = MMU_TYPE_R4000, + }, + { /* A generic CPU supporting MIPS64 Release 6 ISA. FIXME: Support IEEE 754-2008 FP and misaligned memory accesses. Eventually this should be replaced by a real CPU model. */