From patchwork Fri Nov 7 16:56:06 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leon Alrae X-Patchwork-Id: 408213 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id A8FDB1400D2 for ; Sat, 8 Nov 2014 03:59:10 +1100 (AEDT) Received: from localhost ([::1]:32848 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XmmsO-0007Mu-Rm for incoming@patchwork.ozlabs.org; Fri, 07 Nov 2014 11:59:08 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59486) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XmmqD-0003bI-Hs for qemu-devel@nongnu.org; Fri, 07 Nov 2014 11:56:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xmmq6-0006eK-VM for qemu-devel@nongnu.org; Fri, 07 Nov 2014 11:56:53 -0500 Received: from mailapp01.imgtec.com ([195.59.15.196]:55777) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xmmq6-0006eE-PC for qemu-devel@nongnu.org; Fri, 07 Nov 2014 11:56:46 -0500 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id 33D9BEB46449F; Fri, 7 Nov 2014 16:56:42 +0000 (GMT) Received: from lalrae-linux.kl.imgtec.org (192.168.14.163) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.195.1; Fri, 7 Nov 2014 16:56:45 +0000 From: Leon Alrae To: Date: Fri, 7 Nov 2014 16:56:06 +0000 Message-ID: <1415379369-16877-5-git-send-email-leon.alrae@imgtec.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1415379369-16877-1-git-send-email-leon.alrae@imgtec.com> References: <1415379369-16877-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.14.163] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Cc: "Maciej W. Rozycki" Subject: [Qemu-devel] [PULL 4/7] mips: Set the CP0.Config3.DSP and CP0.Config3.DSP2P bits X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: "Maciej W. Rozycki" Set the CP0.Config3.DSP2P bit for the 74kf processor and both that bit and the CP0.Config3.DSP bit for the artificial mips32r5-generic and mips64dspr2 processors. They have the DSPr2 ASE enabled in `insn_flags' and CPUs that implement that ASE need to have both CP0.Config3.DSP and CP0.Config3.DSP2P set or software won't detect its presence. Signed-off-by: Maciej W. Rozycki Reviewed-by: Leon Alrae [leon.alrae@imgtec.com: remove DSP flags from mips32r5-generic] Signed-off-by: Leon Alrae --- target-mips/translate_init.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 4dee1ca..148b394 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -333,7 +333,8 @@ static const mips_def_t mips_defs[] = (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | (1 << CP0C1_CA), .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt) | (1 << CP0C3_DSPP), + .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) | + (0 << CP0C3_VInt), .CP0_LLAddr_rw_bitmask = 0, .CP0_LLAddr_shift = 4, .SYNCI_Step = 32, @@ -376,7 +377,7 @@ static const mips_def_t mips_defs[] = (0x93 << FCR0_PRID), .SEGBITS = 32, .PABITS = 32, - .insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2 | ASE_MSA, + .insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_MSA, .mmu_type = MMU_TYPE_R4000, }, #if defined(TARGET_MIPS64) @@ -601,7 +602,8 @@ static const mips_def_t mips_defs[] = (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA), + .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_DSP2P) | + (1 << CP0C3_DSPP) | (1 << CP0C3_LPA), .CP0_LLAddr_rw_bitmask = 0, .CP0_LLAddr_shift = 0, .SYNCI_Step = 32,