From patchwork Fri Nov 7 16:56:04 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leon Alrae X-Patchwork-Id: 408210 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id D7D6C1400D2 for ; Sat, 8 Nov 2014 03:57:28 +1100 (AEDT) Received: from localhost ([::1]:32835 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xmmql-0004XV-4R for incoming@patchwork.ozlabs.org; Fri, 07 Nov 2014 11:57:27 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59451) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XmmqA-0003WU-Av for qemu-devel@nongnu.org; Fri, 07 Nov 2014 11:56:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xmmq5-0006ds-OJ for qemu-devel@nongnu.org; Fri, 07 Nov 2014 11:56:50 -0500 Received: from mailapp01.imgtec.com ([195.59.15.196]:13266) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xmmq5-0006dn-I0 for qemu-devel@nongnu.org; Fri, 07 Nov 2014 11:56:45 -0500 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id 0481D8B84DED3; Fri, 7 Nov 2014 16:56:41 +0000 (GMT) Received: from lalrae-linux.kl.imgtec.org (192.168.14.163) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.195.1; Fri, 7 Nov 2014 16:56:44 +0000 From: Leon Alrae To: Date: Fri, 7 Nov 2014 16:56:04 +0000 Message-ID: <1415379369-16877-3-git-send-email-leon.alrae@imgtec.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1415379369-16877-1-git-send-email-leon.alrae@imgtec.com> References: <1415379369-16877-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.14.163] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Cc: "Maciej W. Rozycki" Subject: [Qemu-devel] [PULL 2/7] mips: Respect CP0.Status.CU1 for microMIPS FP branches X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: "Maciej W. Rozycki" Make microMIPS FP branches respect CP0.Status.CU1 and trap with a Coprocessor Unusable exception if COP1 has been disabled; also trap if no FPU is present at all. Standard MIPS FP instruction encodings have a more regular structure and branches are covered with a single umbrella along other instructions. This is not the case with the microMIPS encoding, this case has to be taken care of explicitly here. Code to do so has been copied from the standard MIPS code handler for OPC_CP1, in `decode_opc'. Problems arising from this bug will generally only show up on user context switches in operating systems making use of lazy FP context switches, such as Linux. It will also more readily trigger if software FPU emulation is used, either implicitly on a non-float CPU, or forced on a hard-float CPU such as with the "nofpu" Linux kernel command line argument. The problem may have been easily missed because we have no hard-float microMIPS CPU configuration present; in fact we have no microMIPS CPU configuration of any kind present. Signed-off-by: Maciej W. Rozycki Reviewed-by: Leon Alrae Signed-off-by: Leon Alrae --- target-mips/translate.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index 2117ce8..d6722e1 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -13613,8 +13613,13 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx, check_insn(ctx, ASE_MIPS3D); /* Fall through */ do_cp1branch: - gen_compute_branch1(ctx, mips32_op, - (ctx->opcode >> 18) & 0x7, imm << 1); + if (env->CP0_Config1 & (1 << CP0C1_FP)) { + check_cp1_enabled(ctx); + gen_compute_branch1(ctx, mips32_op, + (ctx->opcode >> 18) & 0x7, imm << 1); + } else { + generate_exception_err(ctx, EXCP_CpU, 1); + } break; case BPOSGE64: case BPOSGE32: