From patchwork Mon Nov 3 16:11:35 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leon Alrae X-Patchwork-Id: 406289 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id CB0C714007F for ; Tue, 4 Nov 2014 03:31:29 +1100 (AEDT) Received: from localhost ([::1]:35877 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XlKXP-0005J9-NT for incoming@patchwork.ozlabs.org; Mon, 03 Nov 2014 11:31:27 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46412) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XlKFJ-0004dI-Pj for qemu-devel@nongnu.org; Mon, 03 Nov 2014 11:12:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XlKFE-0005bA-69 for qemu-devel@nongnu.org; Mon, 03 Nov 2014 11:12:45 -0500 Received: from mailapp01.imgtec.com ([195.59.15.196]:62604) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XlKFD-0005ak-Tf for qemu-devel@nongnu.org; Mon, 03 Nov 2014 11:12:40 -0500 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id 24F6057B1F8D for ; Mon, 3 Nov 2014 16:12:36 +0000 (GMT) Received: from virtUbuntuLTP.kl.imgtec.org (192.168.14.163) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.195.1; Mon, 3 Nov 2014 16:12:38 +0000 From: Leon Alrae To: Date: Mon, 3 Nov 2014 16:11:35 +0000 Message-ID: <1415031108-15039-22-git-send-email-leon.alrae@imgtec.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1415031108-15039-1-git-send-email-leon.alrae@imgtec.com> References: <1415031108-15039-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.14.163] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Cc: Yongbok Kim Subject: [Qemu-devel] [PULL 21/34] target-mips: add msa_reset(), global msa register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Yongbok Kim add msa_reset() and global msa register (d type only) Reviewed-by: James Hogan Signed-off-by: Yongbok Kim Signed-off-by: Leon Alrae --- target-mips/translate.c | 56 ++++++++++++++++++++++++++++++++++++++++++++ target-mips/translate_init.c | 34 +++++++++++++++++++++++++++ 2 files changed, 90 insertions(+) diff --git a/target-mips/translate.c b/target-mips/translate.c index 555f89b..baa1826 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -1356,6 +1356,7 @@ static TCGv cpu_dspctrl, btarget, bcond; static TCGv_i32 hflags; static TCGv_i32 fpu_fcr0, fpu_fcr31; static TCGv_i64 fpu_f64[32]; +static TCGv_i64 msa_wr_d[64]; static uint32_t gen_opc_hflags[OPC_BUF_SIZE]; static target_ulong gen_opc_btarget[OPC_BUF_SIZE]; @@ -1454,6 +1455,25 @@ static const char * const fregnames[] = { "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", }; +static const char * const msaregnames[] = { + "w0.d0", "w0.d1", "w1.d0", "w1.d1", + "w2.d0", "w2.d1", "w3.d0", "w3.d1", + "w4.d0", "w4.d1", "w5.d0", "w5.d1", + "w6.d0", "w6.d1", "w7.d0", "w7.d1", + "w8.d0", "w8.d1", "w9.d0", "w9.d1", + "w10.d0", "w10.d1", "w11.d0", "w11.d1", + "w12.d0", "w12.d1", "w13.d0", "w13.d1", + "w14.d0", "w14.d1", "w15.d0", "w15.d1", + "w16.d0", "w16.d1", "w17.d0", "w17.d1", + "w18.d0", "w18.d1", "w19.d0", "w19.d1", + "w20.d0", "w20.d1", "w21.d0", "w21.d1", + "w22.d0", "w22.d1", "w23.d0", "w23.d1", + "w24.d0", "w24.d1", "w25.d0", "w25.d1", + "w26.d0", "w26.d1", "w27.d0", "w27.d1", + "w28.d0", "w28.d1", "w29.d0", "w29.d1", + "w30.d0", "w30.d1", "w31.d0", "w31.d1", +}; + #define MIPS_DEBUG(fmt, ...) \ do { \ if (MIPS_DEBUG_DISAS) { \ @@ -17206,6 +17226,27 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx) } } +/* MIPS SIMD Architecture (MSA) */ +static inline int check_msa_access(DisasContext *ctx) +{ + if (unlikely((ctx->hflags & MIPS_HFLAG_FPU) && + !(ctx->hflags & MIPS_HFLAG_F64))) { + generate_exception(ctx, EXCP_RI); + return 0; + } + + if (unlikely(!(ctx->hflags & MIPS_HFLAG_MSA))) { + if (ctx->insn_flags & ASE_MSA) { + generate_exception(ctx, EXCP_MSADIS); + return 0; + } else { + generate_exception(ctx, EXCP_RI); + return 0; + } + } + return 1; +} + static void decode_opc (CPUMIPSState *env, DisasContext *ctx) { int32_t offset; @@ -18136,6 +18177,15 @@ void mips_tcg_init(void) fpu_f64[i] = tcg_global_mem_new_i64(TCG_AREG0, off, fregnames[i]); } + for (i = 0; i < 32; i++) { + int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); + msa_wr_d[i * 2] = + tcg_global_mem_new_i64(TCG_AREG0, off, msaregnames[i * 2]); + off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]); + msa_wr_d[i * 2 + 1] = + tcg_global_mem_new_i64(TCG_AREG0, off, msaregnames[i * 2 + 1]); + } + cpu_PC = tcg_global_mem_new(TCG_AREG0, offsetof(CPUMIPSState, active_tc.PC), "PC"); for (i = 0; i < MIPS_DSP_ACC; i++) { @@ -18243,6 +18293,7 @@ void cpu_state_reset(CPUMIPSState *env) env->CP0_PageGrain_rw_bitmask = env->cpu_model->CP0_PageGrain_rw_bitmask; env->CP0_PageGrain = env->cpu_model->CP0_PageGrain; env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0; + env->msair = env->cpu_model->MSAIR; env->insn_flags = env->cpu_model->insn_flags; #if defined(CONFIG_USER_ONLY) @@ -18340,6 +18391,11 @@ void cpu_state_reset(CPUMIPSState *env) env->CP0_Status |= (1 << CP0St_FR); } + /* MSA */ + if (env->CP0_Config3 & (1 << CP0C3_MSAP)) { + msa_reset(env); + } + compute_hflags(env); cs->exception_index = EXCP_NONE; } diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 0b70d05..a69a724 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -84,6 +84,7 @@ struct mips_def_t { int32_t CP0_TCStatus_rw_bitmask; int32_t CP0_SRSCtl; int32_t CP1_fcr0; + int32_t MSAIR; int32_t SEGBITS; int32_t PABITS; int32_t CP0_SRSConf0_rw_bitmask; @@ -729,3 +730,36 @@ static void mvp_init (CPUMIPSState *env, const mips_def_t *def) (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) | (0x1 << CP0MVPC1_PCP1); } + +static void msa_reset(CPUMIPSState *env) +{ +#ifdef CONFIG_USER_ONLY + /* MSA access enabled */ + env->CP0_Config5 |= 1 << CP0C5_MSAEn; + env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR); +#endif + + /* MSA CSR: + - non-signaling floating point exception mode off (NX bit is 0) + - Cause, Enables, and Flags are all 0 + - round to nearest / ties to even (RM bits are 0) */ + env->active_tc.msacsr = 0; + + /* tininess detected after rounding.*/ + set_float_detect_tininess(float_tininess_after_rounding, + &env->active_tc.msa_fp_status); + + /* clear float_status exception flags */ + set_float_exception_flags(0, &env->active_tc.msa_fp_status); + + /* set float_status rounding mode */ + set_float_rounding_mode(float_round_nearest_even, + &env->active_tc.msa_fp_status); + + /* set float_status flush modes */ + set_flush_to_zero(0, &env->active_tc.msa_fp_status); + set_flush_inputs_to_zero(0, &env->active_tc.msa_fp_status); + + /* clear float_status nan mode */ + set_default_nan_mode(0, &env->active_tc.msa_fp_status); +}