From patchwork Fri Sep 26 08:08:33 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 393562 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 50693140142 for ; Fri, 26 Sep 2014 18:20:09 +1000 (EST) Received: from localhost ([::1]:45429 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XXQl5-0001fo-EN for incoming@patchwork.ozlabs.org; Fri, 26 Sep 2014 04:20:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39006) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XXQkU-0000fF-70 for qemu-devel@nongnu.org; Fri, 26 Sep 2014 04:19:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XXQkP-0005cq-5t for qemu-devel@nongnu.org; Fri, 26 Sep 2014 04:19:29 -0400 Received: from mail-yk0-x230.google.com ([2607:f8b0:4002:c07::230]:65118) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XXQkP-0005bK-2C for qemu-devel@nongnu.org; Fri, 26 Sep 2014 04:19:25 -0400 Received: by mail-yk0-f176.google.com with SMTP id 19so3709863ykq.35 for ; Fri, 26 Sep 2014 01:19:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=G/pXsfl/jiRUbK/qie2QE7fcFkTg8WKJFiNGm4JYpoU=; b=vPlatRKtEE3TFwLTrsgS09jfNWqbikAs7QUWlUFwantoXM/bY7JOBNulL49cvbfNwG 1hKIZrpWlZ4AFbryKIFk5AY01IyZ4yzjHqBVtc9PlP6T0CpcyX5yZIUnwqul0yvKkixs AjXsogzHZrh2nItzzXVVjFJqp85VcnUKLQ2bluTtiaofwVVLxJTN+YeUChXcV+i2MzxC JzT9ZWtYqL/dCEZy6uSpgwcIrsp/ofj6qUhSZKJ3f/Eqoma6hk1bujNPg+nE1ky6i8Y+ G2P7AFlK1HLk8aG7wW1fG12XPNWQy8w9t8idwWDqj1sF6lSmfoa+5l3Y7AjE2YRfTZOl 7OIA== X-Received: by 10.236.110.168 with SMTP id u28mr18137243yhg.81.1411719559711; Fri, 26 Sep 2014 01:19:19 -0700 (PDT) Received: from localhost ([203.126.243.116]) by mx.google.com with ESMTPSA id b59sm2181453yha.33.2014.09.26.01.19.18 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 26 Sep 2014 01:19:19 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Fri, 26 Sep 2014 18:08:33 +1000 Message-Id: <1411718914-6608-11-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1411718914-6608-1-git-send-email-edgar.iglesias@gmail.com> References: <1411718914-6608-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:4002:c07::230 Cc: rob.herring@linaro.org, peter.crosthwaite@xilinx.com, aggelerf@ethz.ch, serge.fdrv@gmail.com, agraf@suse.de, greg.bellows@linaro.org, pbonzini@redhat.com, alex.bennee@linaro.org, christoffer.dall@linaro.org, rth@twiddle.net Subject: [Qemu-devel] [PATCH v7 10/11] target-arm: Add IRQ and FIQ routing to EL2 and 3 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: "Edgar E. Iglesias" Reviewed-by: Greg Bellows Signed-off-by: Edgar E. Iglesias --- target-arm/cpu.h | 10 ++++++++++ target-arm/helper.c | 17 +++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 4070a38..00b3ad4 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -1179,6 +1179,10 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx) CPUARMState *env = cs->env_ptr; unsigned int cur_el = arm_current_pl(env); unsigned int target_el = arm_excp_target_el(cs, excp_idx); + /* FIXME: Use actual secure state. */ + bool secure = false; + /* If in EL1/0, Physical IRQ routing to EL2 only happens from NS state. */ + bool irq_can_hyp = !secure && cur_el < 2 && target_el == 2; /* Don't take exceptions if they target a lower EL. */ if (cur_el > target_el) { @@ -1187,8 +1191,14 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx) switch (excp_idx) { case EXCP_FIQ: + if (irq_can_hyp && (env->cp15.hcr_el2 & HCR_FMO)) { + return true; + } return !(env->daif & PSTATE_F); case EXCP_IRQ: + if (irq_can_hyp && (env->cp15.hcr_el2 & HCR_IMO)) { + return true; + } return !(env->daif & PSTATE_I) && (!IS_M(env) || env->regs[15] < 0xfffffff0); default: diff --git a/target-arm/helper.c b/target-arm/helper.c index 161c049..c3a70d6 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3656,6 +3656,8 @@ unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx) CPUARMState *env = &cpu->env; unsigned int cur_el = arm_current_pl(env); unsigned int target_el; + /* FIXME: Use actual secure state. */ + bool secure = false; if (!env->aarch64) { /* TODO: Add EL2 and 3 exception handling for AArch32. */ @@ -3670,6 +3672,21 @@ unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx) case EXCP_SMC: target_el = 3; break; + case EXCP_FIQ: + case EXCP_IRQ: + { + const uint64_t hcr_mask = excp_idx == EXCP_FIQ ? HCR_FMO : HCR_IMO; + const uint32_t scr_mask = excp_idx == EXCP_FIQ ? SCR_FIQ : SCR_IRQ; + + target_el = 1; + if (!secure && (env->cp15.hcr_el2 & hcr_mask)) { + target_el = 2; + } + if (env->cp15.scr_el3 & scr_mask) { + target_el = 3; + } + break; + } default: target_el = MAX(cur_el, 1); break;