| Message ID | 1410582564-27687-3-git-send-email-edgar.iglesias@gmail.com |
|---|---|
| State | New |
| Headers | show |
Reviewed-by: Greg Bellows <greg.bellows@linaro.org> On 12 September 2014 21:29, Edgar E. Iglesias <edgar.iglesias@gmail.com> wrote: > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> > > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> > --- > target-arm/cpu.h | 19 ++++++++++++++++++- > target-arm/helper.c | 35 +++++++++++++++++++++++++++++++++-- > 2 files changed, 51 insertions(+), 3 deletions(-) > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index 36507f9..c69d471 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -172,7 +172,6 @@ typedef struct CPUARMState { > uint64_t c1_sys; /* System control register. */ > uint64_t c1_coproc; /* Coprocessor access register. */ > uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ > - uint32_t c1_scr; /* secure config register. */ > uint64_t ttbr0_el1; /* MMU translation table base 0. */ > uint64_t ttbr1_el1; /* MMU translation table base 1. */ > uint64_t c2_control; /* MMU translation table base control. */ > @@ -185,6 +184,7 @@ typedef struct CPUARMState { > uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ > uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ > uint64_t hcr_el2; /* Hypervisor configuration register */ > + uint64_t scr_el3; /* Secure configuration register. */ > uint32_t ifsr_el2; /* Fault status registers. */ > uint64_t esr_el[4]; > uint32_t c6_region[8]; /* MPU base/size registers. */ > @@ -601,6 +601,23 @@ static inline void xpsr_write(CPUARMState *env, > uint32_t val, uint32_t mask) > #define HCR_ID (1ULL << 33) > #define HCR_MASK ((1ULL << 34) - 1) > > +#define SCR_NS (1U << 0) > +#define SCR_IRQ (1U << 1) > +#define SCR_FIQ (1U << 2) > +#define SCR_EA (1U << 3) > +#define SCR_FW (1U << 4) > +#define SCR_AW (1U << 5) > +#define SCR_NET (1U << 6) > +#define SCR_SMD (1U << 7) > +#define SCR_HCE (1U << 8) > +#define SCR_SIF (1U << 9) > +#define SCR_RW (1U << 10) > +#define SCR_ST (1U << 11) > +#define SCR_TWI (1U << 12) > +#define SCR_TWE (1U << 13) > +#define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST)) > +#define SCR_AARCH64_MASK (0x3fff & ~SCR_NET) > + > /* Return the current FPSCR value. */ > uint32_t vfp_get_fpscr(CPUARMState *env); > void vfp_set_fpscr(CPUARMState *env, uint32_t val); > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 40b0c5f..8d0e056 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -747,6 +747,32 @@ static void vbar_write(CPUARMState *env, const > ARMCPRegInfo *ri, > raw_write(env, ri, value & ~0x1FULL); > } > > +static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t > value) > +{ > + /* We only mask off bits that are RES0 both for AArch64 and AArch32. > + * For bits that vary between AArch32/64, code needs to check the > + * current execution mode before directly using the feature bit. > + */ > + uint32_t valid_mask = SCR_AARCH64_MASK | SCR_AARCH32_MASK; > + > + if (!arm_feature(env, ARM_FEATURE_EL2)) { > + valid_mask &= ~SCR_HCE; > + > + /* On ARMv7, SMD (or SCD as it is called in v7) is only > + * supported if EL2 exists. The bit is UNK/SBZP when > + * EL2 is unavailable. In QEMU ARMv7, we force it to always zero > + * when EL2 is unavailable. > + */ > + if (arm_feature(env, ARM_FEATURE_V7)) { > + valid_mask &= ~SCR_SMD; > + } > + } > + > + /* Clear all-context RES0 bits. */ > + value &= valid_mask; > + raw_write(env, ri, value); > +} > + > static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) > { > ARMCPU *cpu = arm_env_get_cpu(env); > @@ -873,8 +899,8 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { > .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]), > .resetvalue = 0 }, > { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, > - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr), > - .resetvalue = 0, }, > + .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, > cp15.scr_el3), > + .resetvalue = 0, .writefn = scr_write }, > { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, > .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, > .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE }, > @@ -2314,6 +2340,11 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = { > .access = PL3_RW, .writefn = vbar_write, > .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]), > .resetvalue = 0 }, > + { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, > + .type = ARM_CP_NO_MIGRATE, > + .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, > + .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, > cp15.scr_el3), > + .writefn = scr_write }, > REGINFO_SENTINEL > }; > > -- > 1.9.1 > >
On 13 September 2014 05:29, Edgar E. Iglesias <edgar.iglesias@gmail.com> wrote: > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> > > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> > --- > target-arm/cpu.h | 19 ++++++++++++++++++- > target-arm/helper.c | 35 +++++++++++++++++++++++++++++++++-- > 2 files changed, 51 insertions(+), 3 deletions(-) > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index 36507f9..c69d471 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -172,7 +172,6 @@ typedef struct CPUARMState { > uint64_t c1_sys; /* System control register. */ > uint64_t c1_coproc; /* Coprocessor access register. */ > uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ > - uint32_t c1_scr; /* secure config register. */ > uint64_t ttbr0_el1; /* MMU translation table base 0. */ > uint64_t ttbr1_el1; /* MMU translation table base 1. */ > uint64_t c2_control; /* MMU translation table base control. */ > @@ -185,6 +184,7 @@ typedef struct CPUARMState { > uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ > uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ > uint64_t hcr_el2; /* Hypervisor configuration register */ > + uint64_t scr_el3; /* Secure configuration register. */ > uint32_t ifsr_el2; /* Fault status registers. */ > uint64_t esr_el[4]; > uint32_t c6_region[8]; /* MPU base/size registers. */ > @@ -873,8 +899,8 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { > .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]), > .resetvalue = 0 }, > { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, > - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr), > - .resetvalue = 0, }, > + .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), > + .resetvalue = 0, .writefn = scr_write }, Still wrong, I'm afraid. For a 32 bit register with a 64 bit struct field you have to use offsetoflow32(), otherwise you'll get the wrong half on bigendian hosts. thanks -- PMM
Is it necessary to make SCR 64-bit if it is 32-bit on both v7 and v8? On 25 September 2014 13:15, Peter Maydell <peter.maydell@linaro.org> wrote: > On 13 September 2014 05:29, Edgar E. Iglesias <edgar.iglesias@gmail.com> > wrote: > > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> > > > > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> > > --- > > target-arm/cpu.h | 19 ++++++++++++++++++- > > target-arm/helper.c | 35 +++++++++++++++++++++++++++++++++-- > > 2 files changed, 51 insertions(+), 3 deletions(-) > > > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > > index 36507f9..c69d471 100644 > > --- a/target-arm/cpu.h > > +++ b/target-arm/cpu.h > > @@ -172,7 +172,6 @@ typedef struct CPUARMState { > > uint64_t c1_sys; /* System control register. */ > > uint64_t c1_coproc; /* Coprocessor access register. */ > > uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. > */ > > - uint32_t c1_scr; /* secure config register. */ > > uint64_t ttbr0_el1; /* MMU translation table base 0. */ > > uint64_t ttbr1_el1; /* MMU translation table base 1. */ > > uint64_t c2_control; /* MMU translation table base control. */ > > @@ -185,6 +184,7 @@ typedef struct CPUARMState { > > uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions > */ > > uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions > */ > > uint64_t hcr_el2; /* Hypervisor configuration register */ > > + uint64_t scr_el3; /* Secure configuration register. */ > > uint32_t ifsr_el2; /* Fault status registers. */ > > uint64_t esr_el[4]; > > uint32_t c6_region[8]; /* MPU base/size registers. */ > > > @@ -873,8 +899,8 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { > > .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]), > > .resetvalue = 0 }, > > { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, > > - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, > cp15.c1_scr), > > - .resetvalue = 0, }, > > + .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, > cp15.scr_el3), > > + .resetvalue = 0, .writefn = scr_write }, > > Still wrong, I'm afraid. For a 32 bit register with a 64 > bit struct field you have to use offsetoflow32(), otherwise > you'll get the wrong half on bigendian hosts. > > thanks > -- PMM >
On 25 September 2014 20:49, Greg Bellows <greg.bellows@linaro.org> wrote:
> Is it necessary to make SCR 64-bit if it is 32-bit on both v7 and v8?
See previous round of reviews -- all AArch64 system registers
are 64 bits ("32 bit" in the ARM ARM is just a shorthand for
"64 bit with the top half RES0"; there is no "read 32 bit
system register instruction) and so the struct fields must
be uint64_t.
thanks
-- PMM
Thanks for the clarification. On 25 September 2014 14:53, Peter Maydell <peter.maydell@linaro.org> wrote: > On 25 September 2014 20:49, Greg Bellows <greg.bellows@linaro.org> wrote: > > Is it necessary to make SCR 64-bit if it is 32-bit on both v7 and v8? > > See previous round of reviews -- all AArch64 system registers > are 64 bits ("32 bit" in the ARM ARM is just a shorthand for > "64 bit with the top half RES0"; there is no "read 32 bit > system register instruction) and so the struct fields must > be uint64_t. > > thanks > -- PMM >
On Thu, Sep 25, 2014 at 07:15:29PM +0100, Peter Maydell wrote: > On 13 September 2014 05:29, Edgar E. Iglesias <edgar.iglesias@gmail.com> wrote: > > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> > > > > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> > > --- > > target-arm/cpu.h | 19 ++++++++++++++++++- > > target-arm/helper.c | 35 +++++++++++++++++++++++++++++++++-- > > 2 files changed, 51 insertions(+), 3 deletions(-) > > > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > > index 36507f9..c69d471 100644 > > --- a/target-arm/cpu.h > > +++ b/target-arm/cpu.h > > @@ -172,7 +172,6 @@ typedef struct CPUARMState { > > uint64_t c1_sys; /* System control register. */ > > uint64_t c1_coproc; /* Coprocessor access register. */ > > uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ > > - uint32_t c1_scr; /* secure config register. */ > > uint64_t ttbr0_el1; /* MMU translation table base 0. */ > > uint64_t ttbr1_el1; /* MMU translation table base 1. */ > > uint64_t c2_control; /* MMU translation table base control. */ > > @@ -185,6 +184,7 @@ typedef struct CPUARMState { > > uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ > > uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ > > uint64_t hcr_el2; /* Hypervisor configuration register */ > > + uint64_t scr_el3; /* Secure configuration register. */ > > uint32_t ifsr_el2; /* Fault status registers. */ > > uint64_t esr_el[4]; > > uint32_t c6_region[8]; /* MPU base/size registers. */ > > > @@ -873,8 +899,8 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { > > .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]), > > .resetvalue = 0 }, > > { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, > > - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr), > > - .resetvalue = 0, }, > > + .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), > > + .resetvalue = 0, .writefn = scr_write }, > > Still wrong, I'm afraid. For a 32 bit register with a 64 > bit struct field you have to use offsetoflow32(), otherwise > you'll get the wrong half on bigendian hosts. Fixed for v7, thanks.
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 36507f9..c69d471 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -172,7 +172,6 @@ typedef struct CPUARMState { uint64_t c1_sys; /* System control register. */ uint64_t c1_coproc; /* Coprocessor access register. */ uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ - uint32_t c1_scr; /* secure config register. */ uint64_t ttbr0_el1; /* MMU translation table base 0. */ uint64_t ttbr1_el1; /* MMU translation table base 1. */ uint64_t c2_control; /* MMU translation table base control. */ @@ -185,6 +184,7 @@ typedef struct CPUARMState { uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ uint64_t hcr_el2; /* Hypervisor configuration register */ + uint64_t scr_el3; /* Secure configuration register. */ uint32_t ifsr_el2; /* Fault status registers. */ uint64_t esr_el[4]; uint32_t c6_region[8]; /* MPU base/size registers. */ @@ -601,6 +601,23 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) #define HCR_ID (1ULL << 33) #define HCR_MASK ((1ULL << 34) - 1) +#define SCR_NS (1U << 0) +#define SCR_IRQ (1U << 1) +#define SCR_FIQ (1U << 2) +#define SCR_EA (1U << 3) +#define SCR_FW (1U << 4) +#define SCR_AW (1U << 5) +#define SCR_NET (1U << 6) +#define SCR_SMD (1U << 7) +#define SCR_HCE (1U << 8) +#define SCR_SIF (1U << 9) +#define SCR_RW (1U << 10) +#define SCR_ST (1U << 11) +#define SCR_TWI (1U << 12) +#define SCR_TWE (1U << 13) +#define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST)) +#define SCR_AARCH64_MASK (0x3fff & ~SCR_NET) + /* Return the current FPSCR value. */ uint32_t vfp_get_fpscr(CPUARMState *env); void vfp_set_fpscr(CPUARMState *env, uint32_t val); diff --git a/target-arm/helper.c b/target-arm/helper.c index 40b0c5f..8d0e056 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -747,6 +747,32 @@ static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, raw_write(env, ri, value & ~0x1FULL); } +static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) +{ + /* We only mask off bits that are RES0 both for AArch64 and AArch32. + * For bits that vary between AArch32/64, code needs to check the + * current execution mode before directly using the feature bit. + */ + uint32_t valid_mask = SCR_AARCH64_MASK | SCR_AARCH32_MASK; + + if (!arm_feature(env, ARM_FEATURE_EL2)) { + valid_mask &= ~SCR_HCE; + + /* On ARMv7, SMD (or SCD as it is called in v7) is only + * supported if EL2 exists. The bit is UNK/SBZP when + * EL2 is unavailable. In QEMU ARMv7, we force it to always zero + * when EL2 is unavailable. + */ + if (arm_feature(env, ARM_FEATURE_V7)) { + valid_mask &= ~SCR_SMD; + } + } + + /* Clear all-context RES0 bits. */ + value &= valid_mask; + raw_write(env, ri, value); +} + static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) { ARMCPU *cpu = arm_env_get_cpu(env); @@ -873,8 +899,8 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]), .resetvalue = 0 }, { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr), - .resetvalue = 0, }, + .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), + .resetvalue = 0, .writefn = scr_write }, { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE }, @@ -2314,6 +2340,11 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = { .access = PL3_RW, .writefn = vbar_write, .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]), .resetvalue = 0 }, + { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, + .type = ARM_CP_NO_MIGRATE, + .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, + .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), + .writefn = scr_write }, REGINFO_SENTINEL };