From patchwork Tue Aug 5 08:50:02 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 376627 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 330F714007B for ; Tue, 5 Aug 2014 18:59:49 +1000 (EST) Received: from localhost ([::1]:57841 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XEaax-0004m6-8d for incoming@patchwork.ozlabs.org; Tue, 05 Aug 2014 04:59:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36237) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XEaaI-00049y-7R for qemu-devel@nongnu.org; Tue, 05 Aug 2014 04:59:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XEaaB-0006WZ-S9 for qemu-devel@nongnu.org; Tue, 05 Aug 2014 04:59:06 -0400 Received: from mail-pd0-x22c.google.com ([2607:f8b0:400e:c02::22c]:46909) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XEaaB-0006W7-8k for qemu-devel@nongnu.org; Tue, 05 Aug 2014 04:58:59 -0400 Received: by mail-pd0-f172.google.com with SMTP id ft15so990482pdb.3 for ; Tue, 05 Aug 2014 01:58:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xTE6OOOGVvu37E/C1trFtVPcVsWyeI8sBH1DI2iwXvY=; b=sI5ybNW+SE7oqgcBpvm53XikXP/RG2xsgc1iI3MiLGBuiZk/UE+QWAw8SaqUIP5Zwf rVWHy4rNYohH3+KylTeer43qq288WIBM7omLYHMV98FaKub14P2FIOCwb5h13CeR7WR9 xqxRetDo05YwAb3UGGox3xkXErlg3DXNe5yRv95RxDT7DLcJRdR+F3h6X26jM/gmiuWr 7+c2zw5Ap/3hrYKpE6LMZM/Zro/rELFrmtFUZnr1+wmwUQZ4a9DmYXzY389I/UUtUbM0 r8ISwNrKP9Th7mSV3vyP8RMdHWg62rXhiEgAbIdTEBIpSO79wg182Lxw8eqlGwc7Ng9d cmDg== X-Received: by 10.67.21.131 with SMTP id hk3mr2527655pad.25.1407229138153; Tue, 05 Aug 2014 01:58:58 -0700 (PDT) Received: from localhost ([203.126.243.116]) by mx.google.com with ESMTPSA id od4sm1286409pbb.70.2014.08.05.01.58.50 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 05 Aug 2014 01:58:57 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Tue, 5 Aug 2014 18:50:02 +1000 Message-Id: <1407228605-27081-9-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1407228605-27081-1-git-send-email-edgar.iglesias@gmail.com> References: <1407228605-27081-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c02::22c Cc: rob.herring@linaro.org, peter.crosthwaite@xilinx.com, aggelerf@ethz.ch, agraf@suse.de, blauwirbel@gmail.com, greg.bellows@linaro.org, pbonzini@redhat.com, alex.bennee@linaro.org, christoffer.dall@linaro.org, rth@twiddle.net Subject: [Qemu-devel] [PATCH v4 08/10] target-arm: A64: Emulate the SMC insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: "Edgar E. Iglesias" Signed-off-by: Edgar E. Iglesias --- target-arm/cpu.h | 1 + target-arm/helper-a64.c | 1 + target-arm/helper.c | 6 ++++++ target-arm/helper.h | 1 + target-arm/internals.h | 6 ++++++ target-arm/op_helper.c | 31 +++++++++++++++++++++++++++++++ target-arm/translate-a64.c | 10 ++++++++++ 7 files changed, 56 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 7fd2f5a..f8e976d 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -52,6 +52,7 @@ #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ #define EXCP_STREX 10 #define EXCP_HVC 11 /* HyperVisor Call */ +#define EXCP_SMC 12 /* Secure Monitor Call */ #define ARMV7M_EXCP_RESET 1 #define ARMV7M_EXCP_NMI 2 diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c index 4e6ca26..996dfea 100644 --- a/target-arm/helper-a64.c +++ b/target-arm/helper-a64.c @@ -477,6 +477,7 @@ void aarch64_cpu_do_interrupt(CPUState *cs) case EXCP_UDEF: case EXCP_SWI: case EXCP_HVC: + case EXCP_SMC: env->cp15.esr_el[new_el] = env->exception.syndrome; break; case EXCP_IRQ: diff --git a/target-arm/helper.c b/target-arm/helper.c index a57a919..a0a210d 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3332,6 +3332,12 @@ unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx) case EXCP_HVC: target_el = MAX(target_el, 2); break; + case EXCP_SMC: + target_el = 3; + if (!secure && cur_el == 1 && (env->cp15.hcr_el2 & HCR_TSC)) { + target_el = 2; + } + break; } return target_el; } diff --git a/target-arm/helper.h b/target-arm/helper.h index 70cfd28..4293453 100644 --- a/target-arm/helper.h +++ b/target-arm/helper.h @@ -51,6 +51,7 @@ DEF_HELPER_3(exception_with_syndrome, void, env, i32, i32) DEF_HELPER_1(wfi, void, env) DEF_HELPER_1(wfe, void, env) DEF_HELPER_2(hvc, void, env, i32) +DEF_HELPER_2(smc, void, env, i32) DEF_HELPER_3(cpsr_write, void, env, i32, i32) DEF_HELPER_1(cpsr_read, i32, env) diff --git a/target-arm/internals.h b/target-arm/internals.h index b08381c..e50a68e 100644 --- a/target-arm/internals.h +++ b/target-arm/internals.h @@ -54,6 +54,7 @@ static const char * const excnames[] = { [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage", [EXCP_STREX] = "QEMU intercept of STREX", [EXCP_HVC] = "Hypervisor Call", + [EXCP_SMC] = "Secure Monitor Call", }; static inline void arm_log_exception(int idx) @@ -210,6 +211,11 @@ static inline uint32_t syn_aa64_hvc(uint32_t imm16) return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); } +static inline uint32_t syn_aa64_smc(uint32_t imm16) +{ + return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); +} + static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_thumb) { return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index d08c6a7..afd1dba 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -404,6 +404,37 @@ void HELPER(hvc)(CPUARMState *env, uint32_t syndrome) raise_exception(env, EXCP_HVC); } +void HELPER(smc)(CPUARMState *env, uint32_t syndrome) +{ + int cur_el = arm_current_pl(env); + /* FIXME: Use real secure state. */ + bool secure = false; + bool smd = env->cp15.scr_el3 & SCR_SMD; + /* On ARMv8 AArch32, SMD only applies to NS mode. + * On ARMv7 SMD only applies to NS mode and only if EL2 is available. + * For ARMv7 non EL2, we force SMD to zero so we don't need to re-check + * the EL2 condition here. + */ + bool udef = is_a64(env) ? smd : !secure && smd; + + /* In NS EL1, HCR controlled routing to EL2 has priority over SMD. */ + if (!secure && cur_el == 1 && (env->cp15.hcr_el2 & HCR_TSC)) { + /* When routing SMCs to EL2, the trap is taken at the SMC insn. */ + env->pc -= 4; + udef = false; + } + + /* We've already checked that EL3 exists at translation time. */ + if (udef) { + /* UDEFs trap on the SMC, roll back to the PC to the SMC insn. */ + env->pc -= 4; + env->exception.syndrome = syn_uncategorized(); + raise_exception(env, EXCP_UDEF); + } + env->exception.syndrome = syndrome; + raise_exception(env, EXCP_SMC); +} + void HELPER(exception_return)(CPUARMState *env) { int cur_el = arm_current_pl(env); diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 9867d14..927bc80 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -1454,6 +1454,16 @@ static void disas_exc(DisasContext *s, uint32_t insn) gen_helper_hvc(cpu_env, tmp); tcg_temp_free_i32(tmp); break; + case 3: + if (!arm_dc_feature(s, ARM_FEATURE_EL3) || s->current_pl == 0) { + unallocated_encoding(s); + break; + } + tmp = tcg_const_i32(syn_aa64_smc(imm16)); + gen_a64_set_pc_im(s->pc); + gen_helper_smc(cpu_env, tmp); + tcg_temp_free_i32(tmp); + break; default: unallocated_encoding(s); break;