From patchwork Tue Aug 5 08:49:57 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 376622 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id ADC9B14009B for ; Tue, 5 Aug 2014 18:55:24 +1000 (EST) Received: from localhost ([::1]:57809 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XEaWh-0007d6-02 for incoming@patchwork.ozlabs.org; Tue, 05 Aug 2014 04:55:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35315) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XEaWD-0006sv-Gc for qemu-devel@nongnu.org; Tue, 05 Aug 2014 04:54:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XEaW8-00055M-N6 for qemu-devel@nongnu.org; Tue, 05 Aug 2014 04:54:53 -0400 Received: from mail-qg0-x232.google.com ([2607:f8b0:400d:c04::232]:58572) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XEaW8-00055I-Hw for qemu-devel@nongnu.org; Tue, 05 Aug 2014 04:54:48 -0400 Received: by mail-qg0-f50.google.com with SMTP id q108so636654qgd.23 for ; Tue, 05 Aug 2014 01:54:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=WqRwIXAfwBtOI0g72yz8/7bLhHwzr8lCt4sTatPEekg=; b=v8H0aQmWcF8cZb/HdEYoa74s0TW4j+Quz5objtUPffObOF5/BscEAC/pzvno/M16cP 52K3sNFOk/2feYW+foYiFzoVT9OmgegQRBUZfLjjyv6oPaBj3R8xpeCXPIrNqKA4bP6K zLs4toDHLlbuLK5F0mhpJAvK2RUXSc7nKiUDWjO2hS4wliABxqXakhgL5gywG6SvTPlJ ItpndStAkSKCdu6jr9YAE7ioHIF7u6OBRv3BP7tcgAe4CLWnizqGuT66cunpPNBL13/7 e8KetovZxOUOsD3h2O3cP/3lhML15T6jC6MrCPpZT/PWHkl7IybbmiYg67BzE0hvreph F8xg== X-Received: by 10.224.122.83 with SMTP id k19mr3274347qar.78.1407228888150; Tue, 05 Aug 2014 01:54:48 -0700 (PDT) Received: from localhost ([203.126.243.116]) by mx.google.com with ESMTPSA id h31sm1256116qge.33.2014.08.05.01.54.41 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 05 Aug 2014 01:54:47 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Tue, 5 Aug 2014 18:49:57 +1000 Message-Id: <1407228605-27081-4-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1407228605-27081-1-git-send-email-edgar.iglesias@gmail.com> References: <1407228605-27081-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400d:c04::232 Cc: rob.herring@linaro.org, peter.crosthwaite@xilinx.com, aggelerf@ethz.ch, agraf@suse.de, blauwirbel@gmail.com, greg.bellows@linaro.org, pbonzini@redhat.com, alex.bennee@linaro.org, christoffer.dall@linaro.org, rth@twiddle.net Subject: [Qemu-devel] [PATCH v4 03/10] target-arm: A64: Refactor aarch64_cpu_do_interrupt X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: "Edgar E. Iglesias" Introduce new_el and new_mode in preparation for future patches that add support for taking exceptions to and from EL2 and 3. No functional change. Reviewed-by: Peter Maydell Signed-off-by: Edgar E. Iglesias --- target-arm/cpu.h | 7 +++++++ target-arm/helper-a64.c | 24 +++++++++++++----------- target-arm/helper.c | 13 +++++++++++++ 3 files changed, 33 insertions(+), 11 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 579570b..2fff2e7 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -476,6 +476,12 @@ int arm_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, #define PSTATE_MODE_EL1t 4 #define PSTATE_MODE_EL0t 0 +/* Map EL and handler into a PSTATE_MODE. */ +static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) +{ + return (el << 2) | handler; +} + /* Return the current PSTATE value. For the moment we don't support 32<->64 bit * interprocessing, so we don't attempt to sync with the cpsr state used by * the 32 bit decoder. @@ -728,6 +734,7 @@ static inline bool arm_el_is_aa64(CPUARMState *env, int el) } void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf); +unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx); /* Interface between CPU and Interrupt controller. */ void armv7m_nvic_set_pending(void *opaque, int irq); diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c index 2e9ef64..4be0784 100644 --- a/target-arm/helper-a64.c +++ b/target-arm/helper-a64.c @@ -443,10 +443,12 @@ void aarch64_cpu_do_interrupt(CPUState *cs) { ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; - target_ulong addr = env->cp15.vbar_el[1]; + unsigned int new_el = arm_excp_target_el(cs, cs->exception_index); + target_ulong addr = env->cp15.vbar_el[new_el]; + unsigned int new_mode = aarch64_pstate_mode(new_el, true); int i; - if (arm_current_pl(env) == 0) { + if (arm_current_pl(env) < new_el) { if (env->aarch64) { addr += 0x400; } else { @@ -464,14 +466,14 @@ void aarch64_cpu_do_interrupt(CPUState *cs) env->exception.syndrome); } - env->cp15.esr_el[1] = env->exception.syndrome; - env->cp15.far_el[1] = env->exception.vaddress; + env->cp15.esr_el[new_el] = env->exception.syndrome; + env->cp15.far_el[new_el] = env->exception.vaddress; switch (cs->exception_index) { case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n", - env->cp15.far_el[1]); + env->cp15.far_el[new_el]); break; case EXCP_BKPT: case EXCP_UDEF: @@ -488,15 +490,15 @@ void aarch64_cpu_do_interrupt(CPUState *cs) } if (is_a64(env)) { - env->banked_spsr[aarch64_banked_spsr_index(1)] = pstate_read(env); + env->banked_spsr[aarch64_banked_spsr_index(new_el)] = pstate_read(env); aarch64_save_sp(env, arm_current_pl(env)); - env->elr_el[1] = env->pc; + env->elr_el[new_el] = env->pc; } else { env->banked_spsr[0] = cpsr_read(env); if (!env->thumb) { - env->cp15.esr_el[1] |= 1 << 25; + env->cp15.esr_el[new_el] |= 1 << 25; } - env->elr_el[1] = env->regs[15]; + env->elr_el[new_el] = env->regs[15]; for (i = 0; i < 15; i++) { env->xregs[i] = env->regs[i]; @@ -505,9 +507,9 @@ void aarch64_cpu_do_interrupt(CPUState *cs) env->condexec_bits = 0; } - pstate_write(env, PSTATE_DAIF | PSTATE_MODE_EL1h); + pstate_write(env, PSTATE_DAIF | new_mode); env->aarch64 = 1; - aarch64_restore_sp(env, 1); + aarch64_restore_sp(env, new_el); env->pc = addr; cs->interrupt_request |= CPU_INTERRUPT_EXITTB; diff --git a/target-arm/helper.c b/target-arm/helper.c index a767380..5bbcb3e 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3242,6 +3242,11 @@ uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode) return 0; } +unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx) +{ + return 1; +} + #else /* Map CPU modes onto saved register banks. */ @@ -3297,6 +3302,14 @@ void switch_mode(CPUARMState *env, int mode) env->spsr = env->banked_spsr[i]; } +/* + * Determine the target EL for a given exception type. + */ +unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx) +{ + return 1; +} + static void v7m_push(CPUARMState *env, uint32_t val) { CPUState *cs = CPU(arm_env_get_cpu(env));