From patchwork Tue Aug 5 08:50:04 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 376629 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 7B0AB14009C for ; Tue, 5 Aug 2014 19:01:27 +1000 (EST) Received: from localhost ([::1]:57855 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XEacX-0006oC-Os for incoming@patchwork.ozlabs.org; Tue, 05 Aug 2014 05:01:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36851) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XEabf-0005u8-6W for qemu-devel@nongnu.org; Tue, 05 Aug 2014 05:00:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XEaba-00079j-Bp for qemu-devel@nongnu.org; Tue, 05 Aug 2014 05:00:31 -0400 Received: from mail-pa0-x22a.google.com ([2607:f8b0:400e:c03::22a]:46633) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XEaba-00079a-1a for qemu-devel@nongnu.org; Tue, 05 Aug 2014 05:00:26 -0400 Received: by mail-pa0-f42.google.com with SMTP id lf10so1038524pab.29 for ; Tue, 05 Aug 2014 02:00:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=aLxqk4ywpo0BZneEX8RYEAVbAdalTXBXA4UtkU+UoRI=; b=kSsp92kwOL5nwJTg5W31+3bPrv32hOiLyJ7XMh/07bMALjzQtbzNMbD3SKkI051vSm HugOB41VZ0YT5BB996azJf/oAHOvf5q7oet4yaD2CARM0wcjyeZYGpncjLSt00zTeaLw yPHH62uaNi1Al2c3l0XQOe7DbvdhR80EX8Tq4rsJOwpkgiMOWrL07WqOCsCvNezgkmaL rrSsXbtHjalg+rpaZOxCvU93USzVHcPAWOmBcwB0TkyZ72Tf0a5/x4OHqqNg+JHm/PLZ rFTHvLlhBW5RKM0au+fe8ZFJk4duzsVOO38hNga51G66eMDkNfLDu48JuDrLWxXyDhDQ xQww== X-Received: by 10.66.66.237 with SMTP id i13mr2627640pat.126.1407229224836; Tue, 05 Aug 2014 02:00:24 -0700 (PDT) Received: from localhost ([203.126.243.116]) by mx.google.com with ESMTPSA id et1sm1297919pbc.39.2014.08.05.02.00.18 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 05 Aug 2014 02:00:24 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Tue, 5 Aug 2014 18:50:04 +1000 Message-Id: <1407228605-27081-11-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1407228605-27081-1-git-send-email-edgar.iglesias@gmail.com> References: <1407228605-27081-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c03::22a Cc: rob.herring@linaro.org, peter.crosthwaite@xilinx.com, aggelerf@ethz.ch, agraf@suse.de, blauwirbel@gmail.com, greg.bellows@linaro.org, pbonzini@redhat.com, alex.bennee@linaro.org, christoffer.dall@linaro.org, rth@twiddle.net Subject: [Qemu-devel] [PATCH v4 10/10] target-arm: Add support for VIRQ and VFIQ X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: "Edgar E. Iglesias" Acked-by: Greg Bellows Signed-off-by: Edgar E. Iglesias --- cpu-exec.c | 12 ++++++++++++ target-arm/cpu.c | 25 +++++++++++++++---------- target-arm/cpu.h | 36 +++++++++++++++++++++++++++++++++--- target-arm/helper-a64.c | 2 ++ target-arm/helper.c | 4 ++++ target-arm/internals.h | 2 ++ 6 files changed, 68 insertions(+), 13 deletions(-) diff --git a/cpu-exec.c b/cpu-exec.c index a579ffc..baf5643 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -498,6 +498,18 @@ int cpu_exec(CPUArchState *env) cc->do_interrupt(cpu); next_tb = 0; } + if (interrupt_request & CPU_INTERRUPT_VIRQ + && arm_excp_unmasked(cpu, EXCP_VIRQ)) { + cpu->exception_index = EXCP_VIRQ; + cc->do_interrupt(cpu); + next_tb = 0; + } + if (interrupt_request & CPU_INTERRUPT_VFIQ + && arm_excp_unmasked(cpu, EXCP_VFIQ)) { + cpu->exception_index = EXCP_VFIQ; + cc->do_interrupt(cpu); + next_tb = 0; + } #elif defined(TARGET_UNICORE32) if (interrupt_request & CPU_INTERRUPT_HARD && !(env->uncached_asr & ASR_I)) { diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 7cebb76..3d7e0bb 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -179,20 +179,22 @@ static void arm_cpu_set_irq(void *opaque, int irq, int level) { ARMCPU *cpu = opaque; CPUState *cs = CPU(cpu); + static const int mask[] = { + [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, + [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, + [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, + [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ + }; switch (irq) { case ARM_CPU_IRQ: - if (level) { - cpu_interrupt(cs, CPU_INTERRUPT_HARD); - } else { - cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); - } - break; case ARM_CPU_FIQ: + case ARM_CPU_VIRQ: + case ARM_CPU_VFIQ: if (level) { - cpu_interrupt(cs, CPU_INTERRUPT_FIQ); + cpu_interrupt(cs, mask[irq]); } else { - cpu_reset_interrupt(cs, CPU_INTERRUPT_FIQ); + cpu_reset_interrupt(cs, mask[irq]); } break; default: @@ -242,9 +244,12 @@ static void arm_cpu_initfn(Object *obj) #ifndef CONFIG_USER_ONLY /* Our inbound IRQ and FIQ lines */ if (kvm_enabled()) { - qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 2); + /* VIRQ and VFIQ are unused with KVM but we add them to maintain + * the same interface as non-KVM CPUs. + */ + qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); } else { - qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 2); + qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); } cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 6e1cb1f..0a6c1b9 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -53,6 +53,8 @@ #define EXCP_STREX 10 #define EXCP_HVC 11 /* HyperVisor Call */ #define EXCP_SMC 12 /* Secure Monitor Call */ +#define EXCP_VIRQ 13 +#define EXCP_VFIQ 14 #define ARMV7M_EXCP_RESET 1 #define ARMV7M_EXCP_NMI 2 @@ -67,6 +69,8 @@ /* ARM-specific interrupt pending bits. */ #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 +#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 +#define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 /* The usual mapping for an AArch64 system register to its AArch32 * counterpart is for the 32 bit world to have access to the lower @@ -82,9 +86,12 @@ #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) #endif -/* Meanings of the ARMCPU object's two inbound GPIO lines */ +/* Meanings of the ARMCPU object's four inbound GPIO lines */ #define ARM_CPU_IRQ 0 #define ARM_CPU_FIQ 1 +#define ARM_CPU_VIRQ 2 +#define ARM_CPU_VFIQ 3 + typedef void ARMWriteCPFunc(void *opaque, int cp_info, int srcreg, int operand, uint32_t value); @@ -1158,6 +1165,18 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx) * EL2 if we are in NS EL0/1. */ bool irq_can_hyp = !secure && cur_el < 2 && target_el == 2; + /* ARMv7-M interrupt return works by loading a magic value + * into the PC. On real hardware the load causes the + * return to occur. The qemu implementation performs the + * jump normally, then does the exception return when the + * CPU tries to execute code at the magic address. + * This will cause the magic PC value to be pushed to + * the stack if an interrupt occurred at the wrong time. + * We avoid this by disabling interrupts when + * pc contains a magic address. + */ + bool irq_unmasked = ((IS_M(env) && env->regs[15] < 0xfffffff0) + || !(env->daif & PSTATE_I)); /* Don't take exceptions if they target a lower EL. */ if (cur_el > target_el) { @@ -1174,8 +1193,19 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx) if (irq_can_hyp && (env->cp15.hcr_el2 & HCR_IMO)) { return true; } - return ((IS_M(env) && env->regs[15] < 0xfffffff0) - || !(env->daif & PSTATE_I)); + return irq_unmasked; + case EXCP_VFIQ: + if (!secure && !(env->cp15.hcr_el2 & HCR_FMO)) { + /* VFIQs are only taken when hypervized and non-secure. */ + return false; + } + return !(env->daif & PSTATE_F); + case EXCP_VIRQ: + if (!secure && !(env->cp15.hcr_el2 & HCR_IMO)) { + /* VIRQs are only taken when hypervized and non-secure. */ + return false; + } + return irq_unmasked; default: g_assert_not_reached(); } diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c index 996dfea..bd16fe3 100644 --- a/target-arm/helper-a64.c +++ b/target-arm/helper-a64.c @@ -481,9 +481,11 @@ void aarch64_cpu_do_interrupt(CPUState *cs) env->cp15.esr_el[new_el] = env->exception.syndrome; break; case EXCP_IRQ: + case EXCP_VIRQ: addr += 0x80; break; case EXCP_FIQ: + case EXCP_VFIQ: addr += 0x100; break; default: diff --git a/target-arm/helper.c b/target-arm/helper.c index 92ee7cd..75f659f 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3352,6 +3352,10 @@ unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx) } break; } + case EXCP_VIRQ: + case EXCP_VFIQ: + target_el = 1; + break; } return target_el; } diff --git a/target-arm/internals.h b/target-arm/internals.h index e50a68e..b1d2d4e 100644 --- a/target-arm/internals.h +++ b/target-arm/internals.h @@ -55,6 +55,8 @@ static const char * const excnames[] = { [EXCP_STREX] = "QEMU intercept of STREX", [EXCP_HVC] = "Hypervisor Call", [EXCP_SMC] = "Secure Monitor Call", + [EXCP_VIRQ] = "Virtual IRQ", + [EXCP_VFIQ] = "Virtual FIQ", }; static inline void arm_log_exception(int idx)