From patchwork Fri Jun 27 15:22:07 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leon Alrae X-Patchwork-Id: 365056 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 6A8C11400DD for ; Sat, 28 Jun 2014 01:33:03 +1000 (EST) Received: from localhost ([::1]:51044 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X0Y97-0005Tr-KC for incoming@patchwork.ozlabs.org; Fri, 27 Jun 2014 11:33:01 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44354) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X0Xzs-0000ET-25 for qemu-devel@nongnu.org; Fri, 27 Jun 2014 11:23:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1X0Xzm-0005Sw-QU for qemu-devel@nongnu.org; Fri, 27 Jun 2014 11:23:27 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:18082) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X0Xzm-0005Sr-G1 for qemu-devel@nongnu.org; Fri, 27 Jun 2014 11:23:22 -0400 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id BD45B1E377299; Fri, 27 Jun 2014 16:23:17 +0100 (IST) Received: from localhost.localdomain (192.168.14.85) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.195.1; Fri, 27 Jun 2014 16:23:20 +0100 From: Leon Alrae To: Date: Fri, 27 Jun 2014 16:22:07 +0100 Message-ID: <1403882530-47821-19-git-send-email-leon.alrae@imgtec.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1403882530-47821-1-git-send-email-leon.alrae@imgtec.com> References: <1403882530-47821-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.14.85] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Cc: yongbok.kim@imgtec.com, cristian.cuna@imgtec.com, leon.alrae@imgtec.com, aurelien@aurel32.net, rth@twiddle.net Subject: [Qemu-devel] [PATCH v3 18/21] target-mips: do not allow Status.FR=0 mode in 64-bit FPU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Status.FR bit must be ignored on write and read as 1 when an implementation of Release 6 of the Architecture in which a 64-bit floating point unit is implemented. Signed-off-by: Leon Alrae Reviewed-by: Yongbok Kim --- v3: * remove line modifying CP0_Status_rw_bitmask as this is done while defining CPU --- target-mips/translate.c | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index a804322..7cfda3d 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -17942,6 +17942,12 @@ void cpu_state_reset(CPUMIPSState *env) } } #endif + if ((env->insn_flags & ISA_MIPS32R6) && + (env->active_fpu.fcr0 & (1 << FCR0_F64))) { + /* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */ + env->CP0_Status |= (1 << CP0St_FR); + } + compute_hflags(env); cs->exception_index = EXCP_NONE; }