From patchwork Fri Jun 20 10:25:47 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Hogan X-Patchwork-Id: 362146 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id B858D140092 for ; Fri, 20 Jun 2014 20:26:27 +1000 (EST) Received: from localhost ([::1]:39968 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wxw1Z-00022U-MC for incoming@patchwork.ozlabs.org; Fri, 20 Jun 2014 06:26:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48806) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wxw1G-0001jJ-Nb for qemu-devel@nongnu.org; Fri, 20 Jun 2014 06:26:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Wxw1C-0000zR-Qa for qemu-devel@nongnu.org; Fri, 20 Jun 2014 06:26:06 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:35872) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wxw1C-0000zF-Ll for qemu-devel@nongnu.org; Fri, 20 Jun 2014 06:26:02 -0400 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id CAE2D1250807F; Fri, 20 Jun 2014 11:25:57 +0100 (IST) Received: from KLMAIL02.kl.imgtec.org (192.168.5.97) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.181.6; Fri, 20 Jun 2014 11:25:59 +0100 Received: from LEMAIL01.le.imgtec.org (192.168.152.62) by klmail02.kl.imgtec.org (192.168.5.97) with Microsoft SMTP Server (TLS) id 14.3.181.6; Fri, 20 Jun 2014 11:25:59 +0100 Received: from jhogan-linux.le.imgtec.org (192.168.154.101) by LEMAIL01.le.imgtec.org (192.168.152.62) with Microsoft SMTP Server (TLS) id 14.3.174.1; Fri, 20 Jun 2014 11:25:59 +0100 From: James Hogan To: Date: Fri, 20 Jun 2014 11:25:47 +0100 Message-ID: <1403259947-32233-1-git-send-email-james.hogan@imgtec.com> X-Mailer: git-send-email 1.9.3 MIME-Version: 1.0 X-Originating-IP: [192.168.154.101] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Cc: Sanjay Lal , James Hogan , Aurelien Jarno Subject: [Qemu-devel] [PATCH v3] hw/mips: gt64xxx_pci: Add VMStateDescription X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Sanjay Lal Add VMStateDescription for GT64120 PCI emulation used by the Malta platform, to allow it to work with savevm/loadvm and live migration. The entire register array is saved/restored using VMSTATE_UINT32_ARRAY (fixed length GT_REGS = 1024). Signed-off-by: Sanjay Lal [james.hogan@imgtec.com: Convert to VMState] Signed-off-by: James Hogan Cc: Aurelien Jarno Reviewed-by: Aurelien Jarno --- This is based on "[Patch 03/12] KVM/MIPS: Add save/restore state APIs for saving/restoring KVM guests."[1]. Changes in v3: - Save entire register array using VMSTATE_UINT32_ARRAY (which is fixed length of GT_REGS = 1024) rather than individual registers. This is safer in case an important register is missed or new emulated functionality is added. (Aurelien Jarno) Changes in v2: - Expand commit message - Convert to VMState (Peter Maydell) [1] https://lists.gnu.org/archive/html/qemu-devel/2013-03/msg00195.html --- hw/mips/gt64xxx_pci.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 6398514c99d2..22f63ce0c8af 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -312,6 +312,27 @@ static void gt64120_pci_mapping(GT64120State *s) } } +static int gt64120_post_load(void *opaque, int version_id) +{ + GT64120State *s = opaque; + + gt64120_isd_mapping(s); + gt64120_pci_mapping(s); + + return 0; +} + +static const VMStateDescription vmstate_gt64120 = { + .name = "gt64120", + .version_id = 1, + .minimum_version_id = 1, + .post_load = gt64120_post_load, + .fields = (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, GT64120State, GT_REGS), + VMSTATE_END_OF_LIST() + } +}; + static void gt64120_writel (void *opaque, hwaddr addr, uint64_t val, unsigned size) { @@ -1174,9 +1195,11 @@ static const TypeInfo gt64120_pci_info = { static void gt64120_class_init(ObjectClass *klass, void *data) { + DeviceClass *dc = DEVICE_CLASS(klass); SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); sdc->init = gt64120_init; + dc->vmsd = &vmstate_gt64120; } static const TypeInfo gt64120_info = {