From patchwork Tue Jun 17 08:45:36 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 360386 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 06F9B140087 for ; Tue, 17 Jun 2014 18:52:08 +1000 (EST) Received: from localhost ([::1]:48182 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wwp7e-0000Su-1J for incoming@patchwork.ozlabs.org; Tue, 17 Jun 2014 04:52:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36251) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wwp6G-0007fm-Pk for qemu-devel@nongnu.org; Tue, 17 Jun 2014 04:50:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Wwp6A-0004dG-UK for qemu-devel@nongnu.org; Tue, 17 Jun 2014 04:50:40 -0400 Received: from mail-pd0-x235.google.com ([2607:f8b0:400e:c02::235]:56008) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wwp6A-0004d2-Oa for qemu-devel@nongnu.org; Tue, 17 Jun 2014 04:50:34 -0400 Received: by mail-pd0-f181.google.com with SMTP id v10so4447868pde.26 for ; Tue, 17 Jun 2014 01:50:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=msBC+rGv3tcfRb068gaET8RmVG6jK0HscZ/vDLer3xM=; b=Meb534+G0SEvTurMC9M8IKhxiyFfE4B/l0CuqKIfze/5nuhKRU57KEpv804g4jNnpl mJ9mlZDErOIFLdXe19+ItV+bLP7nTuGOToQAqT7r61Ts3RLkvpjTjYIibrMfe+zE6dQm TjoPaVd+r7nnFUZlDC+P8lsZY2Knnaf8Y7dNavjU54ZSORSX1oTwZQl4OhscyyWOu/gG akZwFmnDTp8Xh9mh2ttvcAgGIR8YZQY7IVO7Jv5223odC9cG3ZqbBihfV1WSjY/++L/v b9RSRURqoheT7R7/MPELuF3zsQxT6HMkuwmXhXWEXfzso3LwP9z8mMOwO/dO4QML36zH /K3A== X-Received: by 10.68.138.227 with SMTP id qt3mr31288035pbb.6.1402995033949; Tue, 17 Jun 2014 01:50:33 -0700 (PDT) Received: from localhost ([203.126.243.116]) by mx.google.com with ESMTPSA id mt1sm22835104pbb.31.2014.06.17.01.50.27 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 17 Jun 2014 01:50:33 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Tue, 17 Jun 2014 18:45:36 +1000 Message-Id: <1402994746-8328-7-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1402994746-8328-1-git-send-email-edgar.iglesias@gmail.com> References: <1402994746-8328-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c02::235 Cc: rob.herring@linaro.org, peter.crosthwaite@xilinx.com, aggelerf@ethz.ch, agraf@suse.de, blauwirbel@gmail.com, john.williams@xilinx.com, greg.bellows@linaro.org, pbonzini@redhat.com, alex.bennee@linaro.org, christoffer.dall@linaro.org, rth@twiddle.net Subject: [Qemu-devel] [PATCH v3 06/16] target-arm: Add FAR_EL2 and 3 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: "Edgar E. Iglesias" Reviewed-by: Greg Bellows Signed-off-by: Edgar E. Iglesias --- target-arm/cpu.h | 2 +- target-arm/helper.c | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index d1d8c85..1dbed92 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -187,7 +187,7 @@ typedef struct CPUARMState { uint32_t ifsr_el2; /* Fault status registers. */ uint64_t esr_el[4]; uint32_t c6_region[8]; /* MPU base/size registers. */ - uint64_t far_el[2]; /* Fault address registers. */ + uint64_t far_el[4]; /* Fault address registers. */ uint64_t par_el1; /* Translation result. */ uint32_t c9_insn; /* Cache lockdown registers. */ uint32_t c9_data; diff --git a/target-arm/helper.c b/target-arm/helper.c index 94a3b41..7170086 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2120,6 +2120,9 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { .type = ARM_CP_NO_MIGRATE, .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) }, + { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, + .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) }, { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64, .type = ARM_CP_NO_MIGRATE, .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, @@ -2142,6 +2145,9 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = { .type = ARM_CP_NO_MIGRATE, .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0, .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) }, + { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0, + .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) }, { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64, .type = ARM_CP_NO_MIGRATE, .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,