From patchwork Tue Jun 17 08:45:31 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 360381 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id E8BD9140084 for ; Tue, 17 Jun 2014 18:48:40 +1000 (EST) Received: from localhost ([::1]:48155 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wwp4I-0004hn-V7 for incoming@patchwork.ozlabs.org; Tue, 17 Jun 2014 04:48:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35536) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wwp2y-0002ZI-56 for qemu-devel@nongnu.org; Tue, 17 Jun 2014 04:47:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Wwp2t-0003RE-8F for qemu-devel@nongnu.org; Tue, 17 Jun 2014 04:47:16 -0400 Received: from mail-pa0-x229.google.com ([2607:f8b0:400e:c03::229]:41225) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wwp2s-0003R8-VY for qemu-devel@nongnu.org; Tue, 17 Jun 2014 04:47:11 -0400 Received: by mail-pa0-f41.google.com with SMTP id fb1so3043447pad.28 for ; Tue, 17 Jun 2014 01:47:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; bh=6FEQWd5r5Lgkbr6bz0Pj9nrSfgp8NQgsxHN9xLfdoCM=; b=t9L414Vx3aEe2g+ootws91YBjZksZTRRCZv7+ptgR2Qpp5PhwWWB2RRBrvkhVf3M4q EjMXSi/weOsohWdVuMQ2DNf0kBiURDTZ5lpO/88hPnnfyaLhoJWSKgQnun5dwoe6omAG QnzSUB3+OPS15zJXLl7HYK+vdUm3iLJT6algfR/+uM+2ah1Oi6pMugxLL8Hc52uPbYMr eyElmYFnCGixHsHj3KIPz9InFqcVMTnqGBLfbgSoJLu5CfHbfT6khEEAoYRHIgrtMKHl pclGADtnmUmA7KMqgSng2hKDghdj6H+RGEMlWKRWPL6BRY1Uy+KBEhDdpmaXtll/FqZP pnbg== X-Received: by 10.66.231.237 with SMTP id tj13mr30897478pac.136.1402994830041; Tue, 17 Jun 2014 01:47:10 -0700 (PDT) Received: from localhost ([203.126.243.116]) by mx.google.com with ESMTPSA id io8sm22792174pbc.96.2014.06.17.01.47.03 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 17 Jun 2014 01:47:09 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Tue, 17 Jun 2014 18:45:31 +1000 Message-Id: <1402994746-8328-2-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1402994746-8328-1-git-send-email-edgar.iglesias@gmail.com> References: <1402994746-8328-1-git-send-email-edgar.iglesias@gmail.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c03::229 Cc: rob.herring@linaro.org, peter.crosthwaite@xilinx.com, aggelerf@ethz.ch, agraf@suse.de, blauwirbel@gmail.com, john.williams@xilinx.com, greg.bellows@linaro.org, pbonzini@redhat.com, alex.bennee@linaro.org, christoffer.dall@linaro.org, rth@twiddle.net Subject: [Qemu-devel] [PATCH v3 01/16] target-arm: A64: Break out aarch64_save/restore_sp X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: "Edgar E. Iglesias" Break out code to save/restore AArch64 SP into functions. Reviewed-by: Alex Bennée Signed-off-by: Edgar E. Iglesias --- target-arm/internals.h | 29 ++++++++++++++++++++--------- target-arm/kvm64.c | 13 +++---------- target-arm/op_helper.c | 6 +----- 3 files changed, 24 insertions(+), 24 deletions(-) diff --git a/target-arm/internals.h b/target-arm/internals.h index 564b5fa..08fa697 100644 --- a/target-arm/internals.h +++ b/target-arm/internals.h @@ -105,6 +105,24 @@ enum arm_fprounding { int arm_rmode_to_sf(int rmode); +static inline void aarch64_save_sp(CPUARMState *env, int el) +{ + if (env->pstate & PSTATE_SP) { + env->sp_el[el] = env->xregs[31]; + } else { + env->sp_el[0] = env->xregs[31]; + } +} + +static inline void aarch64_restore_sp(CPUARMState *env, int el) +{ + if (env->pstate & PSTATE_SP) { + env->xregs[31] = env->sp_el[el]; + } else { + env->xregs[31] = env->sp_el[0]; + } +} + static inline void update_spsel(CPUARMState *env, uint32_t imm) { unsigned int cur_el = arm_current_pl(env); @@ -114,21 +132,14 @@ static inline void update_spsel(CPUARMState *env, uint32_t imm) if (!((imm ^ env->pstate) & PSTATE_SP)) { return; } + aarch64_save_sp(env, cur_el); env->pstate = deposit32(env->pstate, 0, 1, imm); /* We rely on illegal updates to SPsel from EL0 to get trapped * at translation time. */ assert(cur_el >= 1 && cur_el <= 3); - if (env->pstate & PSTATE_SP) { - /* Switch from using SP_EL0 to using SP_ELx */ - env->sp_el[0] = env->xregs[31]; - env->xregs[31] = env->sp_el[cur_el]; - } else { - /* Switch from SP_EL0 to SP_ELx */ - env->sp_el[cur_el] = env->xregs[31]; - env->xregs[31] = env->sp_el[0]; - } + aarch64_restore_sp(env, cur_el); } /* Valid Syndrome Register EC field values */ diff --git a/target-arm/kvm64.c b/target-arm/kvm64.c index 70f311b..0542cd1 100644 --- a/target-arm/kvm64.c +++ b/target-arm/kvm64.c @@ -21,6 +21,7 @@ #include "sysemu/kvm.h" #include "kvm_arm.h" #include "cpu.h" +#include "internals.h" #include "hw/arm/arm.h" static inline void set_feature(uint64_t *features, int feature) @@ -124,11 +125,7 @@ int kvm_arch_put_registers(CPUState *cs, int level) /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the * QEMU side we keep the current SP in xregs[31] as well. */ - if (env->pstate & PSTATE_SP) { - env->sp_el[1] = env->xregs[31]; - } else { - env->sp_el[0] = env->xregs[31]; - } + aarch64_save_sp(env, 1); reg.id = AARCH64_CORE_REG(regs.sp); reg.addr = (uintptr_t) &env->sp_el[0]; @@ -227,11 +224,7 @@ int kvm_arch_get_registers(CPUState *cs) /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the * QEMU side we keep the current SP in xregs[31] as well. */ - if (env->pstate & PSTATE_SP) { - env->xregs[31] = env->sp_el[1]; - } else { - env->xregs[31] = env->sp_el[0]; - } + aarch64_restore_sp(env, 1); reg.id = AARCH64_CORE_REG(regs.pc); reg.addr = (uintptr_t) &env->pc; diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index 9c1ef52..90a946a 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -376,11 +376,7 @@ void HELPER(exception_return)(CPUARMState *env) uint32_t spsr = env->banked_spsr[spsr_idx]; int new_el, i; - if (env->pstate & PSTATE_SP) { - env->sp_el[cur_el] = env->xregs[31]; - } else { - env->sp_el[0] = env->xregs[31]; - } + aarch64_save_sp(env, cur_el); env->exclusive_addr = -1;