| Message ID | 1402326269-8573-6-git-send-email-edgar.iglesias@gmail.com |
|---|---|
| State | New |
| Headers | show |
Reviewed-by: Greg Bellows <greg.bellows@linaro.org> On 9 June 2014 10:04, Edgar E. Iglesias <edgar.iglesias@gmail.com> wrote: > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> > > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> > --- > target-arm/cpu.h | 2 +- > target-arm/helper.c | 8 ++++++++ > 2 files changed, 9 insertions(+), 1 deletion(-) > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index dca4661..2ee3da2 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -185,7 +185,7 @@ typedef struct CPUARMState { > uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ > uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ > uint32_t ifsr_el2; /* Fault status registers. */ > - uint64_t esr_el[2]; > + uint64_t esr_el[4]; > uint32_t c6_region[8]; /* MPU base/size registers. */ > uint64_t far_el[2]; /* Fault address registers. */ > uint64_t par_el1; /* Translation result. */ > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 2f29a85..6eb7815 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -2116,6 +2116,10 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { > .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1, > .access = PL2_RW, > .fieldoffset = offsetof(CPUARMState, elr_el[2]) }, > + { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64, > + .type = ARM_CP_NO_MIGRATE, > + .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, > + .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, > cp15.esr_el[2]) }, > { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64, > .type = ARM_CP_NO_MIGRATE, > .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, > @@ -2134,6 +2138,10 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = { > .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1, > .access = PL3_RW, > .fieldoffset = offsetof(CPUARMState, elr_el[3]) }, > + { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64, > + .type = ARM_CP_NO_MIGRATE, > + .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0, > + .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, > cp15.esr_el[3]) }, > { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64, > .type = ARM_CP_NO_MIGRATE, > .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0, > -- > 1.8.3.2 > >
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index dca4661..2ee3da2 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -185,7 +185,7 @@ typedef struct CPUARMState { uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ uint32_t ifsr_el2; /* Fault status registers. */ - uint64_t esr_el[2]; + uint64_t esr_el[4]; uint32_t c6_region[8]; /* MPU base/size registers. */ uint64_t far_el[2]; /* Fault address registers. */ uint64_t par_el1; /* Translation result. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index 2f29a85..6eb7815 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2116,6 +2116,10 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1, .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, elr_el[2]) }, + { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64, + .type = ARM_CP_NO_MIGRATE, + .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, + .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) }, { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64, .type = ARM_CP_NO_MIGRATE, .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, @@ -2134,6 +2138,10 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = { .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1, .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, elr_el[3]) }, + { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64, + .type = ARM_CP_NO_MIGRATE, + .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0, + .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) }, { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64, .type = ARM_CP_NO_MIGRATE, .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,