From patchwork Fri May 30 14:47:56 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leon Alrae X-Patchwork-Id: 354214 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 516B81400BE for ; Sat, 31 May 2014 00:58:37 +1000 (EST) Received: from localhost ([::1]:54753 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WqOGR-00016C-Ay for incoming@patchwork.ozlabs.org; Fri, 30 May 2014 10:58:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58752) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WqO7Q-0002ve-53 for qemu-devel@nongnu.org; Fri, 30 May 2014 10:49:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WqO7L-0002Gp-Fc for qemu-devel@nongnu.org; Fri, 30 May 2014 10:49:16 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:4785) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WqO7L-0002Ge-8Z for qemu-devel@nongnu.org; Fri, 30 May 2014 10:49:11 -0400 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id 63EE5E9508323; Fri, 30 May 2014 15:49:06 +0100 (IST) Received: from localhost.localdomain (192.168.14.85) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.181.6; Fri, 30 May 2014 15:49:09 +0100 From: Leon Alrae To: Date: Fri, 30 May 2014 15:47:56 +0100 Message-ID: <1401461279-59617-19-git-send-email-leon.alrae@imgtec.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1401461279-59617-1-git-send-email-leon.alrae@imgtec.com> References: <1401461279-59617-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.14.85] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Cc: yongbok.kim@imgtec.com, cristian.cuna@imgtec.com, leon.alrae@imgtec.com, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH 18/21] target-mips: do not allow Status.FR=0 mode in 64-bit FPU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Status.FR bit must be ignored on write and read as 1 when an implementation of Release 6 of the Architecture in which a 64-bit floating point unit is implemented. Signed-off-by: Leon Alrae --- target-mips/translate.c | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index e609d0c..cc5bd95 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -17930,6 +17930,13 @@ void cpu_state_reset(CPUMIPSState *env) } } #endif + if ((env->insn_flags & ISA_MIPS32R6) && + (env->active_fpu.fcr0 & (1 << FCR0_F64))) { + /* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */ + env->CP0_Status |= (1 << CP0St_FR); + env->CP0_Status_rw_bitmask &= ~(1 << CP0St_FR); + } + compute_hflags(env); cs->exception_index = EXCP_NONE; }