From patchwork Fri May 30 14:47:49 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leon Alrae X-Patchwork-Id: 354208 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 2D8D714008B for ; Sat, 31 May 2014 00:55:32 +1000 (EST) Received: from localhost ([::1]:54723 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WqODR-0004iP-UU for incoming@patchwork.ozlabs.org; Fri, 30 May 2014 10:55:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58694) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WqO7N-0002rG-C7 for qemu-devel@nongnu.org; Fri, 30 May 2014 10:49:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WqO7I-0002Fl-65 for qemu-devel@nongnu.org; Fri, 30 May 2014 10:49:13 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:25972) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WqO7I-0002Fd-14 for qemu-devel@nongnu.org; Fri, 30 May 2014 10:49:08 -0400 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id 0C58E13466E94; Fri, 30 May 2014 15:49:03 +0100 (IST) Received: from localhost.localdomain (192.168.14.85) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.181.6; Fri, 30 May 2014 15:49:05 +0100 From: Leon Alrae To: Date: Fri, 30 May 2014 15:47:49 +0100 Message-ID: <1401461279-59617-12-git-send-email-leon.alrae@imgtec.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1401461279-59617-1-git-send-email-leon.alrae@imgtec.com> References: <1401461279-59617-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.14.85] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Cc: yongbok.kim@imgtec.com, cristian.cuna@imgtec.com, leon.alrae@imgtec.com, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH 11/21] target-mips: Status.UX/SX/KX enable 32-bit address wrapping X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org In R6 the special behaviour for data references is also specified for Kernel and Supervisor mode. Therefore MIPS_HFLAG_UX is replaced by generic MIPS_HFLAG_X indicating whether 64-bit mode is enabled in current operating mode. Signed-off-by: Leon Alrae --- target-mips/cpu.h | 14 ++++++++++---- target-mips/translate.c | 20 +++++++++++++++----- 2 files changed, 25 insertions(+), 9 deletions(-) diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 6c2014e..3dbc219 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -447,7 +447,7 @@ struct CPUMIPSState { and RSQRT.D. */ #define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */ #define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */ -#define MIPS_HFLAG_UX 0x00200 /* 64-bit user mode */ +#define MIPS_HFLAG_X 0x00200 /* 64-bit mode enabled */ #define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */ #define MIPS_HFLAG_M16_SHIFT 10 /* If translation is interrupted between the branch instruction and @@ -721,7 +721,7 @@ static inline void compute_hflags(CPUMIPSState *env) { env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU | - MIPS_HFLAG_UX | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2); + MIPS_HFLAG_X | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2); if (!(env->CP0_Status & (1 << CP0St_EXL)) && !(env->CP0_Status & (1 << CP0St_ERL)) && !(env->hflags & MIPS_HFLAG_DM)) { @@ -733,8 +733,14 @@ static inline void compute_hflags(CPUMIPSState *env) (env->CP0_Status & (1 << CP0St_UX))) { env->hflags |= MIPS_HFLAG_64; } - if (env->CP0_Status & (1 << CP0St_UX)) { - env->hflags |= MIPS_HFLAG_UX; + + if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) && + (env->CP0_Status & (1 << CP0St_UX))) || + (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) && + (env->CP0_Status & (1 << CP0St_SX))) || + (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) && + (env->CP0_Status & (1 << CP0St_KX)))) { + env->hflags |= MIPS_HFLAG_X; } #endif if ((env->CP0_Status & (1 << CP0St_CU0)) || diff --git a/target-mips/translate.c b/target-mips/translate.c index 2e94375..6d294e1 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -1373,17 +1373,27 @@ generate_exception (DisasContext *ctx, int excp) gen_helper_0e0i(raise_exception, excp); } +#if defined(TARGET_MIPS64) +static inline int is_wrapping_needed(DisasContext *ctx) +{ + if (!(ctx->hflags & MIPS_HFLAG_X)) { + /* If not R6 then wrap only in User Mode */ + if ((ctx->insn_flags & ISA_MIPS64R6) || + ((ctx->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM)) { + return 1; + } + } + return 0; +} +#endif + /* Addresses computation */ static inline void gen_op_addr_add (DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1) { tcg_gen_add_tl(ret, arg0, arg1); #if defined(TARGET_MIPS64) - /* For compatibility with 32-bit code, data reference in user mode - with Status_UX = 0 should be casted to 32-bit and sign extended. - See the MIPS64 PRA manual, section 4.10. */ - if (((ctx->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) && - !(ctx->hflags & MIPS_HFLAG_UX)) { + if (is_wrapping_needed(ctx)) { tcg_gen_ext32s_i64(ret, ret); } #endif