From patchwork Fri May 30 07:28:23 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 353908 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44375140092 for ; Fri, 30 May 2014 17:35:18 +1000 (EST) Received: from localhost ([::1]:51906 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WqHLQ-0002K3-6V for incoming@patchwork.ozlabs.org; Fri, 30 May 2014 03:35:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49141) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WqHKu-0001MB-8o for qemu-devel@nongnu.org; Fri, 30 May 2014 03:34:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WqHKn-0005Ti-RW for qemu-devel@nongnu.org; Fri, 30 May 2014 03:34:44 -0400 Received: from mail-pd0-x22c.google.com ([2607:f8b0:400e:c02::22c]:39121) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WqHKn-0005TZ-LI for qemu-devel@nongnu.org; Fri, 30 May 2014 03:34:37 -0400 Received: by mail-pd0-f172.google.com with SMTP id fp1so673987pdb.3 for ; Fri, 30 May 2014 00:34:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GlxasU6lotBVt5uEc9iMsFVNYJudzdbJ3jeo+MPoz1Q=; b=DGSppNSgzDsMEnsxS5D5uLiW+FNhdsER7Cg/EM0T4769BKiV1sRBdsCHj3HmxVnQ3/ 40AxTcu7R0kRTTIR4qF2jHq76mQl3KDU/pRsQhvHEyyZiFMkskMgTZ0yEYIEQSZz+vXI 9JQwWgexj889vyGS0zvXuD4Nwe/+dcuQbezrR3zS2P8qv8mVmdtWgON9ZbMIr1DtD/hJ D0DwS2wxNyDWxV78eUu+SNr2r3lxxMlHyF0MaN/1Y3qmUSvJXMc2T2HrgsBOO7p80T2D B3yLrZ7SULlbqYQLsFL1WYvxJVyfjr/pC1NRZ4GF3sX/VPky71YCydOd4Yqb1JOWqgSI tbLQ== X-Received: by 10.68.215.40 with SMTP id of8mr15851973pbc.15.1401435276703; Fri, 30 May 2014 00:34:36 -0700 (PDT) Received: from localhost ([203.126.243.116]) by mx.google.com with ESMTPSA id wl5sm4843001pbc.13.2014.05.30.00.34.30 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 30 May 2014 00:34:36 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Fri, 30 May 2014 17:28:23 +1000 Message-Id: <1401434911-26992-9-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1401434911-26992-1-git-send-email-edgar.iglesias@gmail.com> References: <1401434911-26992-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c02::22c Cc: rob.herring@linaro.org, peter.crosthwaite@xilinx.com, aggelerf@ethz.ch, agraf@suse.de, blauwirbel@gmail.com, john.williams@xilinx.com, greg.bellows@linaro.org, pbonzini@redhat.com, alex.bennee@linaro.org, christoffer.dall@linaro.org, rth@twiddle.net Subject: [Qemu-devel] [PATCH v1 08/16] target-arm: Add SCR_EL3 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: "Edgar E. Iglesias" Signed-off-by: Edgar E. Iglesias Reviewed-by: Alex Bennée --- target-arm/cpu.h | 15 +++++++++++++++ target-arm/helper.c | 20 ++++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index b446478..28521d4 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -185,6 +185,7 @@ typedef struct CPUARMState { uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ uint64_t hcr_el2; /* Hypervisor configuration register */ + uint32_t scr_el3; /* Secure configuration register. */ uint32_t ifsr_el2; /* Fault status registers. */ uint64_t esr_el[4]; uint32_t c6_region[8]; /* MPU base/size registers. */ @@ -561,6 +562,20 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) #define HCR_ID (1ULL << 33) #define HCR_RES0_MASK ((1ULL << 34) - 1) +#define SCR_NS (1U << 0) +#define SCR_IRQ (1U << 1) +#define SCR_FIQ (1U << 2) +#define SCR_EA (1U << 3) +#define SCR_SMD (1U << 7) +#define SCR_HCE (1U << 8) +#define SCR_SIF (1U << 9) +#define SCR_RW (1U << 10) +#define SCR_ST (1U << 11) +#define SCR_TWI (1U << 12) +#define SCR_TWE (1U << 13) +#define SCR_RES1_MASK (3U << 4) +#define SCR_RES0_MASK (0x3fff & ~SCR_RES1_MASK) + /* Return the current FPSCR value. */ uint32_t vfp_get_fpscr(CPUARMState *env); void vfp_set_fpscr(CPUARMState *env, uint32_t val); diff --git a/target-arm/helper.c b/target-arm/helper.c index cf877ae..b760748 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2162,6 +2162,22 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { REGINFO_SENTINEL }; +static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) +{ + uint32_t res0_mask = SCR_RES0_MASK; + + if (!arm_feature(env, ARM_FEATURE_EL2)) { + res0_mask &= ~SCR_HCE; + } + + /* Set RES1 bits. */ + value |= SCR_RES1_MASK; + + /* Clear RES0 bits. */ + value &= res0_mask; + raw_write(env, ri, value); +} + static const ARMCPRegInfo v8_el3_cp_reginfo[] = { { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64, .type = ARM_CP_NO_MIGRATE, @@ -2184,6 +2200,10 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = { .access = PL3_RW, .writefn = vbar_write, .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]), .resetvalue = 0 }, + { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, + .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), + .writefn = scr_write }, REGINFO_SENTINEL };